riscv/rocket-chip
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add Zscale testing

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Yunsup Lee committed 2015-07-17 12:02:02 -07:00
1 parent 1e977d12f2
commit e7802825c3
7 files changed
+113 -6
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fsim/Makefile
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@@ -17,6 +17,7 @@ output_dir = $(sim_dir)/output
BACKEND ?= fpga
CONFIG ?= DefaultFPGAConfig
TB ?= rocketTestHarness
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag