Add some add'l debug features (#1112)
* debug: Update macros from spec * debug: some corrections in the auto-generated files * debug: update renamed fields * Debug: implement the implicit ebreak option for small program buffers * debug: clean up some unused code and add more require() explanations * debug: make implicit ebreak false * debug: Add the havereset/haveresetack functionality * debug: program buffer can still be 16 even if there is an implicit ebreak
This commit is contained in:
parent
acc8c2bbb3
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@ -44,8 +44,6 @@ object DsbBusConsts {
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object DsbRegAddrs{
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// These may need to move around to be used by the serial interface.
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// These are used by the ROM.
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def HALTED = 0x100
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def GOING = 0x104
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@ -61,8 +59,14 @@ object DsbRegAddrs{
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def DATA = 0x380
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// We want DATA to immediately follow PROGBUF so that we can
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// use them interchangeably.
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def PROGBUF(cfg:DebugModuleParams) = {DATA - (cfg.nProgramBufferWords * 4)}
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// use them interchangeably. Leave another slot if there is an
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// implicit ebreak.
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def PROGBUF(cfg:DebugModuleParams) = {
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val tmp = DATA - (cfg.nProgramBufferWords * 4)
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if (cfg.hasImplicitEbreak) (tmp - 4) else tmp
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}
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// This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF.
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def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 }
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// We want abstract to be immediately before PROGBUF
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// because we auto-generate 2 instructions.
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@ -108,9 +112,11 @@ import DebugAbstractCommandType._
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* nProgamBufferWords: Number of 32-bit words for Program Buffer
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* hasBusMaster: Whethr or not a bus master should be included
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* The size of the accesses supported by the Bus Master.
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* nSerialPorts : Number of serial ports to instantiate
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* supportQuickAccess : Whether or not to support the quick access command.
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* supportHartArray : Whether or not to implement the hart array register.
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* hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping.
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* hartSelToHartId: Provide inverse mapping of the above
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* hasImplicitEbreak: There is an additional RO program buffer word containing an ebreak
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**/
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case class DebugModuleParams (
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@ -125,27 +131,25 @@ case class DebugModuleParams (
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hasAccess32 : Boolean = false,
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hasAccess16 : Boolean = false,
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hasAccess8 : Boolean = false,
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nSerialPorts : Int = 0,
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supportQuickAccess : Boolean = false,
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supportHartArray : Boolean = false,
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hartIdToHartSel : (UInt) => UInt = (x:UInt) => x,
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hartSelToHartId : (UInt) => UInt = (x:UInt) => x
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hartSelToHartId : (UInt) => UInt = (x:UInt) => x,
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hasImplicitEbreak : Boolean = false
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) {
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if (hasBusMaster == false){
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require (hasAccess128 == false)
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require (hasAccess64 == false)
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require (hasAccess32 == false)
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require (hasAccess16 == false)
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require (hasAccess8 == false)
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require (hasAccess128 == false, "No Bus mastering support in Debug Module yet")
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require (hasAccess64 == false, "No Bus mastering support in Debug Module yet")
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require (hasAccess32 == false, "No Bus mastering support in Debug Module yet")
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require (hasAccess16 == false, "No Bus mastering support in Debug Module yet")
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require (hasAccess8 == false, "No Bus mastering support in Debug Module yet")
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}
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require (nSerialPorts <= 8)
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require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}")
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require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32))
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require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16))
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require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16))
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require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}")
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require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}")
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if (supportQuickAccess) {
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// TODO: Check that quick access requirements are met.
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@ -203,6 +207,7 @@ class DMIIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {
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class DebugInternalBundle ()(implicit val p: Parameters) extends ParameterizedBundle()(p) {
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val resumereq = Bool()
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val hartsel = UInt(10.W)
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val ackhavereset = Bool()
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}
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/* structure for top-level Debug Module signals which aren't the bus interfaces.
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@ -328,6 +333,7 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
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DMCONTROLNxt.hartsel := DMCONTROLWrData.hartsel
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DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq
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DMCONTROLNxt.resumereq := DMCONTROLWrData.resumereq
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DMCONTROLNxt.ackhavereset := DMCONTROLWrData.ackhavereset
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}
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}
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@ -380,6 +386,7 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
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io.innerCtrl.valid := DMCONTROLWrEn
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io.innerCtrl.bits.hartsel := DMCONTROLWrData.hartsel
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io.innerCtrl.bits.resumereq := DMCONTROLWrData.resumereq
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io.innerCtrl.bits.ackhavereset := DMCONTROLWrData.ackhavereset
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io.ctrl.ndreset := DMCONTROLReg.ndmreset
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io.ctrl.dmactive := DMCONTROLReg.dmactive
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@ -461,10 +468,9 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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// Sanity Check Configuration For this implementation.
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//--------------------------------------------------------------
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require (cfg.nSerialPorts == 0)
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require (cfg.hasBusMaster == false)
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require (cfg.supportQuickAccess == false)
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require (cfg.supportHartArray == false)
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require (cfg.hasBusMaster == false, "No Bus Mastering support yet")
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require (cfg.supportQuickAccess == false, "No Quick Access support yet")
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require (cfg.supportHartArray == false, "No Hart Array support yet")
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//--------------------------------------------------------------
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// Register & Wire Declarations (which need to be pre-declared)
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@ -472,6 +478,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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val haltedBitRegs = RegInit(Vec.fill(nComponents){false.B})
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val resumeReqRegs = RegInit(Vec.fill(nComponents){false.B})
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val haveResetBitRegs = RegInit(Vec.fill(nComponents){true.B})
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// --- regmapper outputs
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@ -512,7 +519,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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val DMSTATUSRdData = Wire(init = (new DMSTATUSFields()).fromBits(0.U))
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DMSTATUSRdData.authenticated := true.B // Not implemented
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DMSTATUSRdData.versionlo := "b10".U
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DMSTATUSRdData.version := 2.U // Version 0.13
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// Chisel3 Issue #527 , have to do intermediate assignment.
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val unavailVec = Wire(init = Vec.fill(nComponents){false.B})
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@ -531,14 +538,24 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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DMSTATUSRdData.allrunning := true.B
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DMSTATUSRdData.anyrunning := true.B
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}
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DMSTATUSRdData.allhavereset := haveResetBitRegs(selectedHartReg)
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DMSTATUSRdData.anyhavereset := haveResetBitRegs(selectedHartReg)
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val resumereq = io.innerCtrl.fire() && io.innerCtrl.bits.resumereq
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when (io.innerCtrl.fire()){
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when (io.innerCtrl.bits.ackhavereset) {
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haveResetBitRegs(io.innerCtrl.bits.hartsel) := false.B
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}
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}
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DMSTATUSRdData.allresumeack := ~resumeReqRegs(selectedHartReg) && ~resumereq
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DMSTATUSRdData.anyresumeack := ~resumeReqRegs(selectedHartReg) && ~resumereq
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//TODO
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DMSTATUSRdData.cfgstrvalid := false.B
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DMSTATUSRdData.devtreevalid := false.B
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DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B
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//----HARTINFO
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@ -563,7 +580,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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val ABSTRACTCSReset = Wire(init = (new ABSTRACTCSFields()).fromBits(0.U))
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ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U
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ABSTRACTCSReset.progsize := cfg.nProgramBufferWords.U
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ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U
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val ABSTRACTCSReg = Reg(new ABSTRACTCSFields())
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val ABSTRACTCSWrDataVal = Wire(init = 0.U(32.W))
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@ -876,6 +893,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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PROGBUF(cfg)-> programBufferMem.map(x => RegField(8, x)),
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// These sections are read-only.
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IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U)) else Nil},
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WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt)),
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ABSTRACT(cfg) -> abstractGeneratedMem.map{x => RegField.r(32, x)},
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FLAGS -> flags.map{x => RegField.r(8, x.asUInt())},
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@ -2,7 +2,7 @@ package freechips.rocketchip.devices.debug
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import Chisel._
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// This file was auto-generated from the repository at https://github.com/sifive/riscv-debug-spec.git,
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// This file was auto-generated from the repository at https://github.com/riscv/riscv-debug-spec.git,
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// 'make chisel'
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object AC_RegAddrs {
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@ -38,6 +38,9 @@ class ACCESS_REGISTERFields extends Bundle {
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/* 0: Don't do the operation specified by \Fwrite.
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1: Do the operation specified by \Fwrite.
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This bit can be used to just execute the Program Buffer without
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having to worry about placing valid values into \Fsize or \Fregno.
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*/
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val transfer = Bool()
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@ -50,7 +53,10 @@ class ACCESS_REGISTERFields extends Bundle {
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*/
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val write = Bool()
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/* Number of the register to access, as described in Table~\ref{tab:regno}.
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/* Number of the register to access, as described in
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Table~\ref{tab:regno}.
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\Rdpc may be used as an alias for PC if this command is
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supported on a non-halted hart.
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*/
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val regno = UInt(16.W)
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@ -2,7 +2,7 @@ package freechips.rocketchip.devices.debug
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import Chisel._
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// This file was auto-generated from the repository at https://github.com/sifive/riscv-debug-spec.git,
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// This file was auto-generated from the repository at https://github.com/riscv/riscv-debug-spec.git,
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// 'make chisel'
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object DMI_RegAddrs {
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@ -11,6 +11,14 @@ object DMI_RegAddrs {
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This register reports status for the overall debug module
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as well as the currently selected harts, as defined in \Fhasel.
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Harts are nonexistent if they will never be part of this system, no
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matter how long a user waits. Eg. in a simple single-hart system only
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one hart exists, and all others are nonexistent.
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Harts are unavailable if they might exist/become available at a later
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time. Eg. in a multi-hart system some might temporarily be powered
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down, or a system might support hot-swapping harts.
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*/
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def DMI_DMSTATUS = 0x11
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@ -52,8 +60,10 @@ object DMI_RegAddrs {
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def DMI_HAWINDOWSEL = 0x14
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/* This register provides R/W access to a 32-bit portion of the
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hart array mask register. The position of the window is determined by
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\Rhawindowsel.
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hart array mask register.
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The position of the window is determined by \Rhawindowsel. I.e. bit 0
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refers to hart $\Rhawindowsel * 32$, while bit 31 refers to hart
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$\Rhawindowsel * 32 + 31$.
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*/
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def DMI_HAWINDOW = 0x15
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@ -82,27 +92,29 @@ object DMI_RegAddrs {
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*/
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def DMI_ABSTRACTAUTO = 0x18
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/* The Configuration String is described in the RISC-V Priviledged Specification.
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When {\tt cfgstrvalid} is set, reading this register returns bits 31:0 of the configuration
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string address. Reading the other {\tt cfgstraddr} registers returns the upper bits of the
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address.
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/* When {\tt devtreevalid} is set, reading this register returns bits 31:0
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of the Device Tree address. Reading the other {\tt devtreeaddr}
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registers returns the upper bits of the address.
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When system bus mastering is implemented, this should be the
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address that should be used with the System Bus Access module. Otherwise,
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this should be the address that should be used to access the
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config string when \Fhartsel=0.
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When system bus mastering is implemented, this must be an
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address that can be used with the System Bus Access module. Otherwise,
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this must be an address that can be used to access the
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Device Tree from the hart with ID 0.
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If {\tt cfgstrvalid} is 0, then the {\tt cfgstraddr} registers
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If {\tt devtreevalid} is 0, then the {\tt devtreeaddr} registers
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hold identifier information which is not
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further specified in this document.
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The Device Tree itself is described in the RISC-V Privileged
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Specification.
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*/
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def DMI_CFGSTRADDR0 = 0x19
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def DMI_DEVTREEADDR0 = 0x19
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def DMI_CFGSTRADDR1 = 0x1a
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def DMI_DEVTREEADDR1 = 0x1a
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def DMI_CFGSTRADDR2 = 0x1b
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def DMI_DEVTREEADDR2 = 0x1b
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def DMI_CFGSTRADDR3 = 0x1c
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def DMI_DEVTREEADDR3 = 0x1c
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/* Basic read/write registers that may be read or changed by abstract
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commands.
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@ -110,6 +122,8 @@ object DMI_RegAddrs {
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Accessing them while an abstract command is executing causes \Fcmderr
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to be set.
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Attempts to write them while \Fbusy is set does not change their value.
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The values in these registers may not be preserved after an abstract
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command is executed. The only guarantees on their contents are the ones
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offered by the command in question. If the command fails, no
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@ -121,6 +135,11 @@ object DMI_RegAddrs {
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/* The {\tt progbuf} registers provide read/write access to the optional
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program buffer.
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Accessing them while an abstract command is executing causes \Fcmderr
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to be set.
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Attempts to write them while \Fbusy is set does not change their value.
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*/
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def DMI_PROGBUF0 = 0x20
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@ -135,41 +154,12 @@ object DMI_RegAddrs {
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*/
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def DMI_AUTHDATA = 0x30
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/* If \Fserialcount is 0, this register is not present.
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*/
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def DMI_SERCS = 0x34
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/* If \Fserialcount is 0, this register is not present.
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This register provides access to the write data queue of the serial port
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selected by \Fserial in \Rsercs.
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If the {\tt error} bit is not set and the queue is not full, a write to this register
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adds the written data to the core-to-debugger queue.
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Otherwise the {\tt error} bit is set and the write returns error.
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A read to this register returns the last data written.
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*/
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def DMI_SERTX = 0x35
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/* If \Fserialcount is 0, this register is not present.
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This register provides access to the read data queues of the serial port
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selected by \Fserial in \Rsercs.
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If the {\tt error} bit is not set and the queue is not empty, a read from this register reads the
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oldest entry in the debugger-to-core queue, and removes that entry from the queue.
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Otherwise the {\tt error} bit is set and the read returns error.
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*/
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def DMI_SERRX = 0x36
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def DMI_SBCS = 0x38
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/* If \Fsbasize is 0, then this register is not present.
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When the system bus master is busy,
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writes to this register will return error
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and \Fsberror is set.
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writes to this register will set \Fsberror.
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If \Fsberror is 0 and \Fsbautoread is set then the system bus
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master will start
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@ -189,31 +179,31 @@ object DMI_RegAddrs {
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/* If all of the {\tt sbaccess} bits in \Rsbcs are 0, then this register
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is not present.
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If \Fsberror isn't 0 then accesses return error, and don't do anything
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else.
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Any successful system bus read updates the data in this register, and
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marks it no longer stale.
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Writes to this register:
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If \Fsberror isn't 0 then accesses do nothing.
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1. If the bus master is busy then accesses set \Fsberror, return error,
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and don't do anything else.
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\begin{steps}{Writes to this register:}
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\item If the bus master is busy then accesses set \Fsberror, and
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don't do anything else.
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\item Start a bus write of {\tt sbdata} to {\tt sbaddress}.
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\item If \Fsbautoincrement is set, increment {\tt sbaddress}.
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\end{steps}
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2. Update internal data.
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\begin{steps}{Reads from this register:}
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\item If the register is marked stale, then set \Fsberror and don't
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do anything else.
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\item ``Return'' the data.
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\item Mark the register stale.
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\item If \Fsbautoincrement is set, increment {\tt sbaddress}.
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\item If \Fsbautoread is set, start another system bus read.
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\end{steps}
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3. Start a bus write of the internal data to the internal address.
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4. If \Fsbautoincrement is set, increment the internal address.
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Reads to this register:
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1. If bits 31:0 of the internal data register haven't been updated
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since the last time this register was read, then set \Fsberror, return
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error, and don't do anything else.
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2. ``Return'' the data.
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3. If \Fsbautoincrement is set, increment the internal address.
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4. If \Fsbautoread is set, start another system bus read.
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Only \Rsbdatazero has this behavior. The other {\tt sbdata} registers
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have no side effects. On systems that have buses wider than 32 bits, a
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debugger should access \Rsbdatazero after accessing the other {\tt
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sbdata} registers.
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*/
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def DMI_SBDATA0 = 0x3c
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@ -234,13 +224,47 @@ object DMI_RegAddrs {
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class DMSTATUSFields extends Bundle {
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val reserved0 = UInt(14.W)
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val reserved0 = UInt(5.W)
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/* This field is 1 when all currently selected harts have acknowledged the previous \Fresumereq.
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/* Gets set if the Debug Module was accessed incorrectly.
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0 (none): No error.
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1 (badaddr): There was an access to an unimplemented Debug Module
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address.
|
||||
|
||||
7 (other): An access failed for another reason.
|
||||
*/
|
||||
val dmerr = UInt(3.W)
|
||||
|
||||
val reserved1 = UInt(1.W)
|
||||
|
||||
/* If 1, then there is an implicit {\tt ebreak} instruction at the
|
||||
non-existent word immediately after the Program Buffer. This saves
|
||||
the debugger from having to write the {\tt ebreak} itself, and
|
||||
allows the Program Buffer to be one word smaller.
|
||||
|
||||
This must be 1 when \Fprogbufsize is 1.
|
||||
*/
|
||||
val impebreak = Bool()
|
||||
|
||||
val reserved2 = UInt(2.W)
|
||||
|
||||
/* This field is 1 when all currently selected harts have been reset but the reset has not been acknowledged.
|
||||
*/
|
||||
val allhavereset = Bool()
|
||||
|
||||
/* This field is 1 when any currently selected hart has been reset but the reset has not been acknowledged.
|
||||
*/
|
||||
val anyhavereset = Bool()
|
||||
|
||||
/* This field is 1 when all currently selected harts have acknowledged
|
||||
the previous resume request.
|
||||
*/
|
||||
val allresumeack = Bool()
|
||||
|
||||
/* This field is 1 when any currently selected hart has acknowledged the previous \Fresumereq.
|
||||
/* This field is 1 when any currently selected hart has acknowledged
|
||||
the previous resume request.
|
||||
*/
|
||||
val anyresumeack = Bool()
|
||||
|
||||
@ -293,49 +317,58 @@ class DMSTATUSFields extends Bundle {
|
||||
*/
|
||||
val authbusy = Bool()
|
||||
|
||||
val reserved1 = UInt(1.W)
|
||||
val reserved3 = UInt(1.W)
|
||||
|
||||
val cfgstrvalid = Bool()
|
||||
/* 0: \Rdevtreeaddrzero--\Rdevtreeaddrthree hold information which
|
||||
is not relevant to the Device Tree.
|
||||
|
||||
/* Reserved for future use. Reads as 0.
|
||||
1: \Rdevtreeaddrzero--\Rdevtreeaddrthree registers hold the address of the
|
||||
Device Tree.
|
||||
*/
|
||||
val versionhi = UInt(2.W)
|
||||
val devtreevalid = Bool()
|
||||
|
||||
/* 00: There is no Debug Module present.
|
||||
/* 0: There is no Debug Module present.
|
||||
|
||||
01: There is a Debug Module and it conforms to version 0.11 of this
|
||||
1: There is a Debug Module and it conforms to version 0.11 of this
|
||||
specification.
|
||||
|
||||
10: There is a Debug Module and it conforms to version 0.13 of this
|
||||
2: There is a Debug Module and it conforms to version 0.13 of this
|
||||
specification.
|
||||
|
||||
11: Reserved for future use.
|
||||
15: There is a Debug Module but it does not conform to any
|
||||
available version of this spec.
|
||||
*/
|
||||
val versionlo = UInt(2.W)
|
||||
val version = UInt(4.W)
|
||||
|
||||
}
|
||||
|
||||
class DMCONTROLFields extends Bundle {
|
||||
|
||||
/* Halt request signal for all currently selected harts. When set to 1, the
|
||||
hart will halt if it is not currently halted.
|
||||
Setting both \Fhaltreq and \Fresumereq leads to undefined behavior.
|
||||
/* Writes the halt request bit for all currently selected harts.
|
||||
When set to 1, each selected hart will halt if it is not currently
|
||||
halted.
|
||||
|
||||
Writing 1 or 0 has no effect on a hart which is already halted, but
|
||||
the bit must be cleared to 0 before the hart is resumed.
|
||||
|
||||
Writes apply to the new value of \Fhartsel and \Fhasel.
|
||||
*/
|
||||
val haltreq = Bool()
|
||||
|
||||
/* Resume request signal for all currently selected harts. When set to 1,
|
||||
the hart will resume if it is currently halted.
|
||||
Setting both \Fhaltreq and \Fresumereq leads to undefined behavior.
|
||||
/* Writes the resume request bit for all currently selected harts.
|
||||
When set to 1, each selected hart will resume if it is currently
|
||||
halted.
|
||||
|
||||
The resume request bit is ignored while the halt request bit is
|
||||
set.
|
||||
|
||||
Writes apply to the new value of \Fhartsel and \Fhasel.
|
||||
*/
|
||||
val resumereq = Bool()
|
||||
|
||||
/* This optional bit controls reset to all the currently selected harts.
|
||||
To perform a reset the debugger writes 1, and then writes 0 to
|
||||
deassert the reset signal.
|
||||
/* This optional field writes the reset bit for all the currently
|
||||
selected harts. To perform a reset the debugger writes 1, and then
|
||||
writes 0 to deassert the reset signal.
|
||||
|
||||
If this feature is not implemented, the bit always stays 0, so
|
||||
after writing 1 the debugger can read the register back to see if
|
||||
@ -345,7 +378,14 @@ class DMCONTROLFields extends Bundle {
|
||||
*/
|
||||
val hartreset = Bool()
|
||||
|
||||
val reserved0 = UInt(2.W)
|
||||
/* Writing 1 to this bit clears the {\tt havereset} bits for
|
||||
any selected harts.
|
||||
|
||||
Writes apply to the new value of \Fhartsel and \Fhasel.
|
||||
*/
|
||||
val ackhavereset = Bool()
|
||||
|
||||
val reserved0 = UInt(1.W)
|
||||
|
||||
/* Selects the definition of currently selected harts.
|
||||
|
||||
@ -369,7 +409,11 @@ class DMCONTROLFields extends Bundle {
|
||||
val reserved1 = UInt(14.W)
|
||||
|
||||
/* This bit controls the reset signal from the DM to the rest of the
|
||||
system. To perform a reset the debugger writes 1, and then writes 0
|
||||
system. The signal should reset every part of the system, including
|
||||
every hart, except for the DM and any logic required to access the
|
||||
DM.
|
||||
To perform a system reset the debugger writes 1,
|
||||
and then writes 0
|
||||
to deassert the reset.
|
||||
*/
|
||||
val ndmreset = Bool()
|
||||
@ -386,8 +430,8 @@ class DMCONTROLFields extends Bundle {
|
||||
Debug Module after power up, including the platform's system reset
|
||||
or Debug Transport reset signals.
|
||||
|
||||
A debugger should pulse this bit low to ensure that the Debug
|
||||
Module is fully reset and ready to use.
|
||||
A debugger may pulse this bit low to get the debug module into a
|
||||
known state.
|
||||
|
||||
Implementations may use this bit to aid debugging, for example by
|
||||
preventing the Debug Module from being power gated while debugging
|
||||
@ -431,7 +475,7 @@ class HARTINFOFields extends Bundle {
|
||||
shadowing the {\tt data} registers.
|
||||
|
||||
If \Fdataaccess is 1: Signed address of RAM where the {\tt data}
|
||||
registers are shadowed.
|
||||
registers are shadowed, to be used to access relative to \Rzero.
|
||||
*/
|
||||
val dataaddr = UInt(12.W)
|
||||
|
||||
@ -524,11 +568,8 @@ class ABSTRACTCSFields extends Bundle {
|
||||
val reserved0 = UInt(3.W)
|
||||
|
||||
/* Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16.
|
||||
|
||||
TODO: Explain what can be done with each size of the buffer, to suggest
|
||||
why you would want more or less words.
|
||||
*/
|
||||
val progsize = UInt(5.W)
|
||||
val progbufsize = UInt(5.W)
|
||||
|
||||
val reserved1 = UInt(11.W)
|
||||
|
||||
@ -547,8 +588,9 @@ class ABSTRACTCSFields extends Bundle {
|
||||
|
||||
0 (none): No error.
|
||||
|
||||
1 (busy): An abstract command was executing while \Rcommand or one
|
||||
of the {\tt data} registers was accessed.
|
||||
1 (busy): An abstract command was executing while \Rcommand,
|
||||
\Rabstractcs, \Rabstractauto was written, or when one
|
||||
of the {\tt data} or {\tt progbuf} registers was read or written.
|
||||
|
||||
2 (not supported): The requested command is not supported. A
|
||||
command that is not supported while the hart is running may be
|
||||
@ -567,7 +609,7 @@ class ABSTRACTCSFields extends Bundle {
|
||||
val reserved3 = UInt(3.W)
|
||||
|
||||
/* Number of {\tt data} registers that are implemented as part of the
|
||||
abstract command interface. Valid sizes are 0 - 8.
|
||||
abstract command interface. Valid sizes are 0 - 12.
|
||||
*/
|
||||
val datacount = UInt(5.W)
|
||||
|
||||
@ -603,7 +645,7 @@ class ABSTRACTAUTOFields extends Bundle {
|
||||
|
||||
}
|
||||
|
||||
class CFGSTRADDR0Fields extends Bundle {
|
||||
class DEVTREEADDR0Fields extends Bundle {
|
||||
|
||||
val addr = UInt(32.W)
|
||||
|
||||
@ -627,88 +669,6 @@ class AUTHDATAFields extends Bundle {
|
||||
|
||||
}
|
||||
|
||||
class SERCSFields extends Bundle {
|
||||
|
||||
/* Number of supported serial ports.
|
||||
*/
|
||||
val serialcount = UInt(4.W)
|
||||
|
||||
val reserved0 = UInt(1.W)
|
||||
|
||||
/* Select which serial port is accessed by \Rserrx and \Rsertx.
|
||||
*/
|
||||
val serial = UInt(3.W)
|
||||
|
||||
val error7 = Bool()
|
||||
|
||||
val valid7 = Bool()
|
||||
|
||||
val full7 = Bool()
|
||||
|
||||
val error6 = Bool()
|
||||
|
||||
val valid6 = Bool()
|
||||
|
||||
val full6 = Bool()
|
||||
|
||||
val error5 = Bool()
|
||||
|
||||
val valid5 = Bool()
|
||||
|
||||
val full5 = Bool()
|
||||
|
||||
val error4 = Bool()
|
||||
|
||||
val valid4 = Bool()
|
||||
|
||||
val full4 = Bool()
|
||||
|
||||
val error3 = Bool()
|
||||
|
||||
val valid3 = Bool()
|
||||
|
||||
val full3 = Bool()
|
||||
|
||||
val error2 = Bool()
|
||||
|
||||
val valid2 = Bool()
|
||||
|
||||
val full2 = Bool()
|
||||
|
||||
val error1 = Bool()
|
||||
|
||||
val valid1 = Bool()
|
||||
|
||||
val full1 = Bool()
|
||||
|
||||
/* 1 when the debugger-to-core queue for serial port 0 has
|
||||
over or underflowed. This bit will remain set until it is reset by
|
||||
writing 1 to this bit.
|
||||
*/
|
||||
val error0 = Bool()
|
||||
|
||||
/* 1 when the core-to-debugger queue for serial port 0 is not empty.
|
||||
*/
|
||||
val valid0 = Bool()
|
||||
|
||||
/* 1 when the debugger-to-core queue for serial port 0 is full.
|
||||
*/
|
||||
val full0 = Bool()
|
||||
|
||||
}
|
||||
|
||||
class SERTXFields extends Bundle {
|
||||
|
||||
val data = UInt(32.W)
|
||||
|
||||
}
|
||||
|
||||
class SERRXFields extends Bundle {
|
||||
|
||||
val data = UInt(32.W)
|
||||
|
||||
}
|
||||
|
||||
class SBCSFields extends Bundle {
|
||||
|
||||
val reserved0 = UInt(11.W)
|
||||
@ -731,20 +691,18 @@ class SBCSFields extends Bundle {
|
||||
|
||||
4: 128-bit
|
||||
|
||||
If an unsupported system bus access size is written here,
|
||||
the DM may not perform the access, or may perform the access
|
||||
with any access size.
|
||||
If an unsupported system bus access size is written here, the DM
|
||||
does not perform the access and sberror is set to 3.
|
||||
*/
|
||||
val sbaccess = UInt(3.W)
|
||||
|
||||
/* When 1, the internal address value (used by the system bus master)
|
||||
is incremented by the access size (in bytes) selected in \Fsbaccess
|
||||
after every system bus access.
|
||||
/* When 1, {\tt sbaddress} is incremented by the access size (in
|
||||
bytes) selected in \Fsbaccess after every system bus access.
|
||||
*/
|
||||
val sbautoincrement = Bool()
|
||||
|
||||
/* When 1, every read from \Rsbdatazero automatically triggers a system
|
||||
bus read at the new address.
|
||||
/* When 1, every read from \Rsbdatazero automatically triggers a
|
||||
system bus read at the (possibly auto-incremented) address.
|
||||
*/
|
||||
val sbautoread = Bool()
|
||||
|
||||
@ -762,10 +720,9 @@ class SBCSFields extends Bundle {
|
||||
|
||||
3: There was some other error (eg. alignment).
|
||||
|
||||
4: The system bus master was busy when a one of the
|
||||
4: The system bus master was busy when one of the
|
||||
{\tt sbaddress} or {\tt sbdata} registers was written,
|
||||
or the {\tt sbdata} register was read when it had
|
||||
stale data.
|
||||
or \Rsbdatazero was read when it had stale data.
|
||||
*/
|
||||
val sberror = UInt(3.W)
|
||||
|
||||
@ -798,7 +755,7 @@ class SBCSFields extends Bundle {
|
||||
|
||||
class SBADDRESS0Fields extends Bundle {
|
||||
|
||||
/* Accesses bits 31:0 of the internal address.
|
||||
/* Accesses bits 31:0 of the physical address in {\tt sbaddress}.
|
||||
*/
|
||||
val address = UInt(32.W)
|
||||
|
||||
@ -806,8 +763,8 @@ class SBADDRESS0Fields extends Bundle {
|
||||
|
||||
class SBADDRESS1Fields extends Bundle {
|
||||
|
||||
/* Accesses bits 63:32 of the internal address (if the system address
|
||||
bus is that wide).
|
||||
/* Accesses bits 63:32 of the physical address in {\tt sbaddress} (if
|
||||
the system address bus is that wide).
|
||||
*/
|
||||
val address = UInt(32.W)
|
||||
|
||||
@ -815,8 +772,8 @@ class SBADDRESS1Fields extends Bundle {
|
||||
|
||||
class SBADDRESS2Fields extends Bundle {
|
||||
|
||||
/* Accesses bits 95:64 of the internal address (if the system address
|
||||
bus is that wide).
|
||||
/* Accesses bits 95:64 of the physical address in {\tt sbaddress} (if
|
||||
the system address bus is that wide).
|
||||
*/
|
||||
val address = UInt(32.W)
|
||||
|
||||
@ -824,7 +781,7 @@ class SBADDRESS2Fields extends Bundle {
|
||||
|
||||
class SBDATA0Fields extends Bundle {
|
||||
|
||||
/* Accesses bits 31:0 of the internal data.
|
||||
/* Accesses bits 31:0 of {\tt sbdata}.
|
||||
*/
|
||||
val data = UInt(32.W)
|
||||
|
||||
@ -832,8 +789,8 @@ class SBDATA0Fields extends Bundle {
|
||||
|
||||
class SBDATA1Fields extends Bundle {
|
||||
|
||||
/* Accesses bits 63:32 of the internal data (if the system bus is
|
||||
that wide).
|
||||
/* Accesses bits 63:32 of {\tt sbdata} (if the system bus is that
|
||||
wide).
|
||||
*/
|
||||
val data = UInt(32.W)
|
||||
|
||||
@ -841,8 +798,8 @@ class SBDATA1Fields extends Bundle {
|
||||
|
||||
class SBDATA2Fields extends Bundle {
|
||||
|
||||
/* Accesses bits 95:64 of the internal data (if the system bus is
|
||||
that wide).
|
||||
/* Accesses bits 95:64 of {\tt sbdata} (if the system bus is that
|
||||
wide).
|
||||
*/
|
||||
val data = UInt(32.W)
|
||||
|
||||
@ -850,8 +807,8 @@ class SBDATA2Fields extends Bundle {
|
||||
|
||||
class SBDATA3Fields extends Bundle {
|
||||
|
||||
/* Accesses bits 127:96 of the internal data (if the system bus is
|
||||
that wide).
|
||||
/* Accesses bits 127:96 of {\tt sbdata} (if the system bus is that
|
||||
wide).
|
||||
*/
|
||||
val data = UInt(32.W)
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user