riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Fix "make run-asm-tests" for Chisel 3

Browse Source 
This was just a missing Makefrag-verilog dependency (the .d file).
This commit is contained in:
Palmer Dabbelt 2016-06-06 15:02:54 -07:00 committed by Andrew Waterman
parent 2c17f828b6
commit e6c4372332
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
vsim/Makefrag-verilog
View File

@ -21,10 +21,10 @@ $(FIRRTL):
# files. # files.
.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir .SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
$(generated_dir)/%.$(CONFIG).fir: $(chisel_srcs) $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
mkdir -p $(dir $@) mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(patsubst %.$(CONFIG).fir,%,$(notdir $@)) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem" cd $(base_dir) && $(SBT) "run $(PROJECT) $(patsubst %.$(CONFIG).fir,%,$(patsubst %.d,%.fir,$(notdir $@))) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem"
mv $(patsubst %.$(CONFIG).fir,%.fir,$@) $@ mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
$(generated_dir)/%.v $(generated_dir)/%.prm: $(generated_dir)/%.fir $(FIRRTL) $(generated_dir)/%.v $(generated_dir)/%.prm: $(generated_dir)/%.fir $(FIRRTL)
mkdir -p $(dir $@) mkdir -p $(dir $@)