1
0

Merge pull request #276 from ucb-bar/nmemchannels-fix

Pass nMemChannels to coreplex through CoreplexConfig
This commit is contained in:
Andrew Waterman 2016-09-12 14:05:50 -07:00 committed by GitHub
commit e66abb5e92
3 changed files with 8 additions and 7 deletions

View File

@ -14,8 +14,6 @@ import rocket.Util._
import java.nio.{ByteBuffer,ByteOrder} import java.nio.{ByteBuffer,ByteOrder}
import java.nio.file.{Files, Paths} import java.nio.file.{Files, Paths}
/** Function for building Coreplex */
case object BuildCoreplex extends Field[(Parameters, CoreplexConfig) => Coreplex]
/** Number of memory channels */ /** Number of memory channels */
case object NMemoryChannels extends Field[Int] case object NMemoryChannels extends Field[Int]
/** Number of banks per memory channel */ /** Number of banks per memory channel */
@ -31,9 +29,7 @@ case object BootROMFile extends Field[String]
trait HasCoreplexParameters { trait HasCoreplexParameters {
implicit val p: Parameters implicit val p: Parameters
lazy val nMemChannels = p(NMemoryChannels)
lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel) lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
lazy val nBanks = nMemChannels*nBanksPerMemChannel
lazy val lsb = p(BankIdLSB) lazy val lsb = p(BankIdLSB)
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" }) lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" }) lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
@ -46,6 +42,7 @@ case class CoreplexConfig(
nTiles: Int, nTiles: Int,
nExtInterrupts: Int, nExtInterrupts: Int,
nSlaves: Int, nSlaves: Int,
nMemChannels: Int,
hasSupervisor: Boolean, hasSupervisor: Boolean,
hasExtMMIOPort: Boolean) hasExtMMIOPort: Boolean)
{ {
@ -56,7 +53,7 @@ abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConf
with HasCoreplexParameters { with HasCoreplexParameters {
class CoreplexIO(implicit val p: Parameters, implicit val c: CoreplexConfig) extends Bundle { class CoreplexIO(implicit val p: Parameters, implicit val c: CoreplexConfig) extends Bundle {
val master = new Bundle { val master = new Bundle {
val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)) val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
val mmio = c.hasExtMMIOPort.option(new ClientUncachedTileLinkIO()(outermostMMIOParams)) val mmio = c.hasExtMMIOPort.option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
} }
val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
@ -78,6 +75,7 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
} }
val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _) val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _) val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
val nBanks = tc.nMemChannels * nBanksPerMemChannel
// Build an uncore backing the Tiles // Build an uncore backing the Tiles
buildUncore(p.alterPartial({ buildUncore(p.alterPartial({
@ -116,7 +114,7 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
// Create a converter between TileLinkIO and MemIO for each channel // Create a converter between TileLinkIO and MemIO for each channel
val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outermostParams)) val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, tc.nMemChannels)(outermostParams))
val outerTLParams = p.alterPartial({ case TLId => "L2toMC" }) val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
val backendBuffering = TileLinkDepths(0,0,0,0,0) val backendBuffering = TileLinkDepths(0,0,0,0,0)

View File

@ -9,7 +9,7 @@ import cde.Parameters
class UnitTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) { class UnitTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
require(!tc.hasExtMMIOPort) require(!tc.hasExtMMIOPort)
require(tc.nSlaves == 0) require(tc.nSlaves == 0)
require(nMemChannels == 0) require(tc.nMemChannels == 0)
io.debug.req.ready := Bool(false) io.debug.req.ready := Bool(false)
io.debug.resp.valid := Bool(false) io.debug.resp.valid := Bool(false)

View File

@ -16,6 +16,8 @@ import coreplex._
case object GlobalAddrMap extends Field[GlobalVariable[AddrMap]] case object GlobalAddrMap extends Field[GlobalVariable[AddrMap]]
case object ConfigString extends Field[GlobalVariable[String]] case object ConfigString extends Field[GlobalVariable[String]]
case object NCoreplexExtClients extends Field[GlobalVariable[Int]] case object NCoreplexExtClients extends Field[GlobalVariable[Int]]
/** Function for building Coreplex */
case object BuildCoreplex extends Field[(Parameters, CoreplexConfig) => Coreplex]
/** Base Top with no Periphery */ /** Base Top with no Periphery */
abstract class BaseTop(val p: Parameters) extends LazyModule { abstract class BaseTop(val p: Parameters) extends LazyModule {
@ -36,6 +38,7 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
nTiles = p(NTiles), nTiles = p(NTiles),
nExtInterrupts = outer.pInterrupts.sum, nExtInterrupts = outer.pInterrupts.sum,
nSlaves = outer.pBusMasters.sum, nSlaves = outer.pBusMasters.sum,
nMemChannels = p(NMemoryChannels),
hasSupervisor = p(UseVM), hasSupervisor = p(UseVM),
hasExtMMIOPort = !(outer.pDevices.get.isEmpty && p(ExtMMIOPorts).isEmpty) hasExtMMIOPort = !(outer.pDevices.get.isEmpty && p(ExtMMIOPorts).isEmpty)
) )