diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala
index 0f882603..70d1343b 100644
--- a/src/main/scala/coreplex/Coreplex.scala
+++ b/src/main/scala/coreplex/Coreplex.scala
@@ -14,8 +14,6 @@ import rocket.Util._
 import java.nio.{ByteBuffer,ByteOrder}
 import java.nio.file.{Files, Paths}
 
-/** Function for building Coreplex */
-case object BuildCoreplex extends Field[(Parameters, CoreplexConfig) => Coreplex]
 /** Number of memory channels */
 case object NMemoryChannels extends Field[Int]
 /** Number of banks per memory channel */
@@ -31,9 +29,7 @@ case object BootROMFile extends Field[String]
 
 trait HasCoreplexParameters {
   implicit val p: Parameters
-  lazy val nMemChannels = p(NMemoryChannels)
   lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
-  lazy val nBanks = nMemChannels*nBanksPerMemChannel
   lazy val lsb = p(BankIdLSB)
   lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
   lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
@@ -46,6 +42,7 @@ case class CoreplexConfig(
     nTiles: Int,
     nExtInterrupts: Int,
     nSlaves: Int,
+    nMemChannels: Int,
     hasSupervisor: Boolean,
     hasExtMMIOPort: Boolean)
 {
@@ -56,7 +53,7 @@ abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConf
     with HasCoreplexParameters {
   class CoreplexIO(implicit val p: Parameters, implicit val c: CoreplexConfig) extends Bundle {
     val master = new Bundle {
-      val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
+      val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
       val mmio = c.hasExtMMIOPort.option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
     }
     val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
@@ -78,6 +75,7 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
   }
   val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
   val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
+  val nBanks = tc.nMemChannels * nBanksPerMemChannel
 
   // Build an uncore backing the Tiles
   buildUncore(p.alterPartial({
@@ -116,7 +114,7 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
     l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
 
     // Create a converter between TileLinkIO and MemIO for each channel
-    val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outermostParams))
+    val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, tc.nMemChannels)(outermostParams))
 
     val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
     val backendBuffering = TileLinkDepths(0,0,0,0,0)
diff --git a/src/main/scala/coreplex/UnitTest.scala b/src/main/scala/coreplex/UnitTest.scala
index 66b2e0e3..0e91d697 100644
--- a/src/main/scala/coreplex/UnitTest.scala
+++ b/src/main/scala/coreplex/UnitTest.scala
@@ -9,7 +9,7 @@ import cde.Parameters
 class UnitTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
   require(!tc.hasExtMMIOPort)
   require(tc.nSlaves == 0)
-  require(nMemChannels == 0)
+  require(tc.nMemChannels == 0)
 
   io.debug.req.ready := Bool(false)
   io.debug.resp.valid := Bool(false)
diff --git a/src/main/scala/rocketchip/Top.scala b/src/main/scala/rocketchip/Top.scala
index daa6a5ea..1e031ee1 100644
--- a/src/main/scala/rocketchip/Top.scala
+++ b/src/main/scala/rocketchip/Top.scala
@@ -16,6 +16,8 @@ import coreplex._
 case object GlobalAddrMap extends Field[GlobalVariable[AddrMap]]
 case object ConfigString extends Field[GlobalVariable[String]]
 case object NCoreplexExtClients extends Field[GlobalVariable[Int]]
+/** Function for building Coreplex */
+case object BuildCoreplex extends Field[(Parameters, CoreplexConfig) => Coreplex]
 
 /** Base Top with no Periphery */
 abstract class BaseTop(val p: Parameters) extends LazyModule {
@@ -36,6 +38,7 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
     nTiles = p(NTiles),
     nExtInterrupts = outer.pInterrupts.sum,
     nSlaves = outer.pBusMasters.sum,
+    nMemChannels = p(NMemoryChannels),
     hasSupervisor = p(UseVM),
     hasExtMMIOPort = !(outer.pDevices.get.isEmpty && p(ExtMMIOPorts).isEmpty)
   )