riscv/rocket-chip
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FrontBus: attach to splitter for cross-chip visibility

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This commit is contained in:
Wesley W. Terpstra 2017-09-05 15:02:16 -07:00
parent 5886025b1a
commit e65f49b89a
2 changed files with 4 additions and 2 deletions
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4
src/main/scala/coreplex/FrontBus.scala
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@ -12,7 +12,7 @@ case class FrontBusParams(
beatBytes: Int, beatBytes: Int,
blockBytes: Int, blockBytes: Int,
masterBuffering: BufferParams = BufferParams.default, masterBuffering: BufferParams = BufferParams.default,
slaveBuffering: BufferParams = BufferParams.none slaveBuffering: BufferParams = BufferParams.default
) extends TLBusParams ) extends TLBusParams
case object FrontBusParams extends Field[FrontBusParams] case object FrontBusParams extends Field[FrontBusParams]
@ -56,6 +56,6 @@ trait HasFrontBus extends HasSystemBus {
val fbus = new FrontBus(frontbusParams) val fbus = new FrontBus(frontbusParams)
sbus.bufferFromMasters := fbus.toSystemBus sbus.fromFrontBus := fbus.toSystemBus
} }

2
src/main/scala/coreplex/SystemBus.scala
View File

@ -49,6 +49,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def fromCoherentChip: TLInwardNode = inwardNode def fromCoherentChip: TLInwardNode = inwardNode
def fromFrontBus: TLInwardNode = master_splitter.node
def fromSyncTiles(params: BufferParams, addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = { def fromSyncTiles(params: BufferParams, addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
val tile_buf = LazyModule(new TLBuffer(params)) val tile_buf = LazyModule(new TLBuffer(params))
name.foreach { n => tile_buf.suggestName(s"${busName}_${n}_TLBuffer") } name.foreach { n => tile_buf.suggestName(s"${busName}_${n}_TLBuffer") }