diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
index 3fd080d9..6e4b3883 100644
--- a/src/main/scala/coreplex/FrontBus.scala
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -12,7 +12,7 @@ case class FrontBusParams(
   beatBytes: Int,
   blockBytes: Int,
   masterBuffering: BufferParams = BufferParams.default,
-  slaveBuffering: BufferParams = BufferParams.none
+  slaveBuffering: BufferParams = BufferParams.default
 ) extends TLBusParams
 
 case object FrontBusParams extends Field[FrontBusParams]
@@ -56,6 +56,6 @@ trait HasFrontBus extends HasSystemBus {
 
   val fbus = new FrontBus(frontbusParams)
 
-  sbus.bufferFromMasters := fbus.toSystemBus
+  sbus.fromFrontBus := fbus.toSystemBus
 
 }
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 6f0a371d..5b7b771b 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -49,6 +49,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def fromCoherentChip: TLInwardNode = inwardNode
 
+  def fromFrontBus: TLInwardNode = master_splitter.node
+
   def fromSyncTiles(params: BufferParams, addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
     val tile_buf = LazyModule(new TLBuffer(params))
     name.foreach { n => tile_buf.suggestName(s"${busName}_${n}_TLBuffer") }