riscv/rocket-chip
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don't update xact_vol_irel if not a voluntary irel

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This commit is contained in:
Howard Mao 2016-07-18 17:05:23 -07:00
parent 84098db81f
commit e5cccc0526
1 changed files with 5 additions and 3 deletions
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2
uncore/src/main/scala/agents/Trackers.scala
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@ -257,9 +257,11 @@ trait AcceptsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer {
val irel_fire = (irel_is_allocating || irel_is_merging) && io.inner.release.ready val irel_fire = (irel_is_allocating || irel_is_merging) && io.inner.release.ready
when (irel_fire) { when (irel_fire) {
when (io.irel().first()) { when (io.irel().first()) {
when (io.irel().isVoluntary()) {
xact_vol_ir_r_type := io.irel().r_type xact_vol_ir_r_type := io.irel().r_type
xact_vol_ir_src := io.irel().client_id xact_vol_ir_src := io.irel().client_id
xact_vol_ir_client_xact_id := io.irel().client_xact_id xact_vol_ir_client_xact_id := io.irel().client_xact_id
}
// If this release has data, set all the pending bits except the first. // If this release has data, set all the pending bits except the first.
// Otherwise, clear all the pending bits // Otherwise, clear all the pending bits
pending_irel_data := Mux(io.irel().hasMultibeatData(), pending_irel_data := Mux(io.irel().hasMultibeatData(),