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rocketchip: work-around ucb-bar/chisel3#472

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This commit is contained in:
Wesley W. Terpstra
2017-01-31 13:54:02 -08:00
parent 9c0cc6fdf4
commit e5af59db68
14 changed files with 223 additions and 223 deletions
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28
src/main/scala/uncore/axi4/Protocol.scala
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@ -17,21 +17,21 @@ object AXI4Parameters
val qosBits = 4
val respBits = 2
val CACHE_RALLOCATE = UInt(8, width = cacheBits)
val CACHE_WALLOCATE = UInt(4, width = cacheBits)
val CACHE_MODIFIABLE = UInt(2, width = cacheBits)
val CACHE_BUFFERABLE = UInt(1, width = cacheBits)
def CACHE_RALLOCATE = UInt(8, width = cacheBits)
def CACHE_WALLOCATE = UInt(4, width = cacheBits)
def CACHE_MODIFIABLE = UInt(2, width = cacheBits)
def CACHE_BUFFERABLE = UInt(1, width = cacheBits)
val PROT_PRIVILEDGED = UInt(1, width = protBits)
val PROT_INSECURE = UInt(2, width = protBits)
val PROT_INSTRUCTION = UInt(4, width = protBits)
def PROT_PRIVILEDGED = UInt(1, width = protBits)
def PROT_INSECURE = UInt(2, width = protBits)
def PROT_INSTRUCTION = UInt(4, width = protBits)
val BURST_FIXED = UInt(0, width = burstBits)
val BURST_INCR = UInt(1, width = burstBits)
val BURST_WRAP = UInt(2, width = burstBits)
def BURST_FIXED = UInt(0, width = burstBits)
def BURST_INCR = UInt(1, width = burstBits)
def BURST_WRAP = UInt(2, width = burstBits)
val RESP_OKAY = UInt(0, width = respBits)
val RESP_EXOKAY = UInt(1, width = respBits)
val RESP_SLVERR = UInt(2, width = respBits)
val RESP_DECERR = UInt(3, width = respBits)
def RESP_OKAY = UInt(0, width = respBits)
def RESP_EXOKAY = UInt(1, width = respBits)
def RESP_SLVERR = UInt(2, width = respBits)
def RESP_DECERR = UInt(3, width = respBits)
}