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rocketchip: work-around ucb-bar/chisel3#472

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This commit is contained in:
Wesley W. Terpstra
2017-01-31 13:54:02 -08:00
parent 9c0cc6fdf4
commit e5af59db68
14 changed files with 223 additions and 223 deletions
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6
src/main/scala/uncore/apb/Protocol.scala
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@ -9,8 +9,8 @@ object APBParameters
// These are all fixed by the AHB standard:
val protBits = 3
val PROT_PRIVILEDGED = UInt(1, width = protBits)
val PROT_NONSECURE = UInt(2, width = protBits)
val PROT_INSTRUCTION = UInt(4, width = protBits)
def PROT_PRIVILEDGED = UInt(1, width = protBits)
def PROT_NONSECURE = UInt(2, width = protBits)
def PROT_INSTRUCTION = UInt(4, width = protBits)
def PROT_DEFAULT = PROT_PRIVILEDGED
}