riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

rocketchip: work-around ucb-bar/chisel3#472

Browse Source
This commit is contained in:
Wesley W. Terpstra
2017-01-31 13:54:02 -08:00
parent 9c0cc6fdf4
commit e5af59db68
14 changed files with 223 additions and 223 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
src/main/scala/uncore/ahb/Protocol.scala
View File

@ -12,28 +12,28 @@ object AHBParameters
val protBits = 4
val sizeBits = 3 // 8*2^s
val TRANS_IDLE = UInt(0, width = transBits) // No transfer requested, not in a burst
val TRANS_BUSY = UInt(1, width = transBits) // No transfer requested, in a burst
val TRANS_NONSEQ = UInt(2, width = transBits) // First (potentially only) request in a burst
val TRANS_SEQ = UInt(3, width = transBits) // Following requests in a burst
def TRANS_IDLE = UInt(0, width = transBits) // No transfer requested, not in a burst
def TRANS_BUSY = UInt(1, width = transBits) // No transfer requested, in a burst
def TRANS_NONSEQ = UInt(2, width = transBits) // First (potentially only) request in a burst
def TRANS_SEQ = UInt(3, width = transBits) // Following requests in a burst
val BURST_SINGLE = UInt(0, width = burstBits) // Single access (no burst)
val BURST_INCR = UInt(1, width = burstBits) // Incrementing burst of arbitrary length, not crossing 1KB
val BURST_WRAP4 = UInt(2, width = burstBits) // 4-beat wrapping burst
val BURST_INCR4 = UInt(3, width = burstBits) // 4-beat incrementing burst
val BURST_WRAP8 = UInt(4, width = burstBits) // 8-beat wrapping burst
val BURST_INCR8 = UInt(5, width = burstBits) // 8-beat incrementing burst
val BURST_WRAP16 = UInt(6, width = burstBits) // 16-beat wrapping burst
val BURST_INCR16 = UInt(7, width = burstBits) // 16-beat incrementing burst
def BURST_SINGLE = UInt(0, width = burstBits) // Single access (no burst)
def BURST_INCR = UInt(1, width = burstBits) // Incrementing burst of arbitrary length, not crossing 1KB
def BURST_WRAP4 = UInt(2, width = burstBits) // 4-beat wrapping burst
def BURST_INCR4 = UInt(3, width = burstBits) // 4-beat incrementing burst
def BURST_WRAP8 = UInt(4, width = burstBits) // 8-beat wrapping burst
def BURST_INCR8 = UInt(5, width = burstBits) // 8-beat incrementing burst
def BURST_WRAP16 = UInt(6, width = burstBits) // 16-beat wrapping burst
def BURST_INCR16 = UInt(7, width = burstBits) // 16-beat incrementing burst
val maxTransfer = 16
val RESP_OKAY = Bool(false)
val RESP_ERROR = Bool(true)
def RESP_OKAY = Bool(false)
def RESP_ERROR = Bool(true)
val PROT_DATA = UInt(1, width = protBits)
val PROT_PRIVILEDGED = UInt(2, width = protBits)
val PROT_BUFFERABLE = UInt(4, width = protBits)
val PROT_CACHEABLE = UInt(8, width = protBits)
def PROT_DATA = UInt(1, width = protBits)
def PROT_PRIVILEDGED = UInt(2, width = protBits)
def PROT_BUFFERABLE = UInt(4, width = protBits)
def PROT_CACHEABLE = UInt(8, width = protBits)
def PROT_DEFAULT = PROT_DATA | PROT_PRIVILEDGED
}