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rocketchip: work-around ucb-bar/chisel3#472

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This commit is contained in:
Wesley W. Terpstra
2017-01-31 13:54:02 -08:00
parent 9c0cc6fdf4
commit e5af59db68
14 changed files with 223 additions and 223 deletions
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40
src/main/scala/uncore/Consts.scala
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@@ -9,26 +9,26 @@ object MemoryOpConstants extends MemoryOpConstants
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
val M_X = BitPat("b?????");
val M_XRD = UInt("b00000"); // int load
val M_XWR = UInt("b00001"); // int store
val M_PFR = UInt("b00010"); // prefetch with intent to read
val M_PFW = UInt("b00011"); // prefetch with intent to write
val M_XA_SWAP = UInt("b00100");
val M_FLUSH_ALL = UInt("b00101") // flush all lines
val M_XLR = UInt("b00110");
val M_XSC = UInt("b00111");
val M_XA_ADD = UInt("b01000");
val M_XA_XOR = UInt("b01001");
val M_XA_OR = UInt("b01010");
val M_XA_AND = UInt("b01011");
val M_XA_MIN = UInt("b01100");
val M_XA_MAX = UInt("b01101");
val M_XA_MINU = UInt("b01110");
val M_XA_MAXU = UInt("b01111");
val M_FLUSH = UInt("b10000") // write back dirty data and cede R/W permissions
val M_PRODUCE = UInt("b10001") // write back dirty data and cede W permissions
val M_CLEAN = UInt("b10011") // write back dirty data and retain R/W permissions
def M_X = BitPat("b?????");
def M_XRD = UInt("b00000"); // int load
def M_XWR = UInt("b00001"); // int store
def M_PFR = UInt("b00010"); // prefetch with intent to read
def M_PFW = UInt("b00011"); // prefetch with intent to write
def M_XA_SWAP = UInt("b00100");
def M_FLUSH_ALL = UInt("b00101") // flush all lines
def M_XLR = UInt("b00110");
def M_XSC = UInt("b00111");
def M_XA_ADD = UInt("b01000");
def M_XA_XOR = UInt("b01001");
def M_XA_OR = UInt("b01010");
def M_XA_AND = UInt("b01011");
def M_XA_MIN = UInt("b01100");
def M_XA_MAX = UInt("b01101");
def M_XA_MINU = UInt("b01110");
def M_XA_MAXU = UInt("b01111");
def M_FLUSH = UInt("b10000") // write back dirty data and cede R/W permissions
def M_PRODUCE = UInt("b10001") // write back dirty data and cede W permissions
def M_CLEAN = UInt("b10011") // write back dirty data and retain R/W permissions
def isAMO(cmd: UInt) = cmd(3) || cmd === M_XA_SWAP
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW