riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

rocketchip: work-around ucb-bar/chisel3#472

Browse Source
This commit is contained in:
Wesley W. Terpstra
2017-01-31 13:54:02 -08:00
parent 9c0cc6fdf4
commit e5af59db68
14 changed files with 223 additions and 223 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
src/main/scala/uncore/Consts.scala
View File

@ -9,26 +9,26 @@ object MemoryOpConstants extends MemoryOpConstants
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
val M_X = BitPat("b?????");
val M_XRD = UInt("b00000"); // int load
val M_XWR = UInt("b00001"); // int store
val M_PFR = UInt("b00010"); // prefetch with intent to read
val M_PFW = UInt("b00011"); // prefetch with intent to write
val M_XA_SWAP = UInt("b00100");
val M_FLUSH_ALL = UInt("b00101") // flush all lines
val M_XLR = UInt("b00110");
val M_XSC = UInt("b00111");
val M_XA_ADD = UInt("b01000");
val M_XA_XOR = UInt("b01001");
val M_XA_OR = UInt("b01010");
val M_XA_AND = UInt("b01011");
val M_XA_MIN = UInt("b01100");
val M_XA_MAX = UInt("b01101");
val M_XA_MINU = UInt("b01110");
val M_XA_MAXU = UInt("b01111");
val M_FLUSH = UInt("b10000") // write back dirty data and cede R/W permissions
val M_PRODUCE = UInt("b10001") // write back dirty data and cede W permissions
val M_CLEAN = UInt("b10011") // write back dirty data and retain R/W permissions
def M_X = BitPat("b?????");
def M_XRD = UInt("b00000"); // int load
def M_XWR = UInt("b00001"); // int store
def M_PFR = UInt("b00010"); // prefetch with intent to read
def M_PFW = UInt("b00011"); // prefetch with intent to write
def M_XA_SWAP = UInt("b00100");
def M_FLUSH_ALL = UInt("b00101") // flush all lines
def M_XLR = UInt("b00110");
def M_XSC = UInt("b00111");
def M_XA_ADD = UInt("b01000");
def M_XA_XOR = UInt("b01001");
def M_XA_OR = UInt("b01010");
def M_XA_AND = UInt("b01011");
def M_XA_MIN = UInt("b01100");
def M_XA_MAX = UInt("b01101");
def M_XA_MINU = UInt("b01110");
def M_XA_MAXU = UInt("b01111");
def M_FLUSH = UInt("b10000") // write back dirty data and cede R/W permissions
def M_PRODUCE = UInt("b10001") // write back dirty data and cede W permissions
def M_CLEAN = UInt("b10011") // write back dirty data and retain R/W permissions
def isAMO(cmd: UInt) = cmd(3) || cmd === M_XA_SWAP
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW

36
src/main/scala/uncore/ahb/Protocol.scala
View File

@ -12,28 +12,28 @@ object AHBParameters
val protBits = 4
val sizeBits = 3 // 8*2^s
val TRANS_IDLE = UInt(0, width = transBits) // No transfer requested, not in a burst
val TRANS_BUSY = UInt(1, width = transBits) // No transfer requested, in a burst
val TRANS_NONSEQ = UInt(2, width = transBits) // First (potentially only) request in a burst
val TRANS_SEQ = UInt(3, width = transBits) // Following requests in a burst
def TRANS_IDLE = UInt(0, width = transBits) // No transfer requested, not in a burst
def TRANS_BUSY = UInt(1, width = transBits) // No transfer requested, in a burst
def TRANS_NONSEQ = UInt(2, width = transBits) // First (potentially only) request in a burst
def TRANS_SEQ = UInt(3, width = transBits) // Following requests in a burst
val BURST_SINGLE = UInt(0, width = burstBits) // Single access (no burst)
val BURST_INCR = UInt(1, width = burstBits) // Incrementing burst of arbitrary length, not crossing 1KB
val BURST_WRAP4 = UInt(2, width = burstBits) // 4-beat wrapping burst
val BURST_INCR4 = UInt(3, width = burstBits) // 4-beat incrementing burst
val BURST_WRAP8 = UInt(4, width = burstBits) // 8-beat wrapping burst
val BURST_INCR8 = UInt(5, width = burstBits) // 8-beat incrementing burst
val BURST_WRAP16 = UInt(6, width = burstBits) // 16-beat wrapping burst
val BURST_INCR16 = UInt(7, width = burstBits) // 16-beat incrementing burst
def BURST_SINGLE = UInt(0, width = burstBits) // Single access (no burst)
def BURST_INCR = UInt(1, width = burstBits) // Incrementing burst of arbitrary length, not crossing 1KB
def BURST_WRAP4 = UInt(2, width = burstBits) // 4-beat wrapping burst
def BURST_INCR4 = UInt(3, width = burstBits) // 4-beat incrementing burst
def BURST_WRAP8 = UInt(4, width = burstBits) // 8-beat wrapping burst
def BURST_INCR8 = UInt(5, width = burstBits) // 8-beat incrementing burst
def BURST_WRAP16 = UInt(6, width = burstBits) // 16-beat wrapping burst
def BURST_INCR16 = UInt(7, width = burstBits) // 16-beat incrementing burst
val maxTransfer = 16
val RESP_OKAY = Bool(false)
val RESP_ERROR = Bool(true)
def RESP_OKAY = Bool(false)
def RESP_ERROR = Bool(true)
val PROT_DATA = UInt(1, width = protBits)
val PROT_PRIVILEDGED = UInt(2, width = protBits)
val PROT_BUFFERABLE = UInt(4, width = protBits)
val PROT_CACHEABLE = UInt(8, width = protBits)
def PROT_DATA = UInt(1, width = protBits)
def PROT_PRIVILEDGED = UInt(2, width = protBits)
def PROT_BUFFERABLE = UInt(4, width = protBits)
def PROT_CACHEABLE = UInt(8, width = protBits)
def PROT_DEFAULT = PROT_DATA | PROT_PRIVILEDGED
}

6
src/main/scala/uncore/apb/Protocol.scala
View File

@ -9,8 +9,8 @@ object APBParameters
// These are all fixed by the AHB standard:
val protBits = 3
val PROT_PRIVILEDGED = UInt(1, width = protBits)
val PROT_NONSECURE = UInt(2, width = protBits)
val PROT_INSTRUCTION = UInt(4, width = protBits)
def PROT_PRIVILEDGED = UInt(1, width = protBits)
def PROT_NONSECURE = UInt(2, width = protBits)
def PROT_INSTRUCTION = UInt(4, width = protBits)
def PROT_DEFAULT = PROT_PRIVILEDGED
}

28
src/main/scala/uncore/axi4/Protocol.scala
View File

@ -17,21 +17,21 @@ object AXI4Parameters
val qosBits = 4
val respBits = 2
val CACHE_RALLOCATE = UInt(8, width = cacheBits)
val CACHE_WALLOCATE = UInt(4, width = cacheBits)
val CACHE_MODIFIABLE = UInt(2, width = cacheBits)
val CACHE_BUFFERABLE = UInt(1, width = cacheBits)
def CACHE_RALLOCATE = UInt(8, width = cacheBits)
def CACHE_WALLOCATE = UInt(4, width = cacheBits)
def CACHE_MODIFIABLE = UInt(2, width = cacheBits)
def CACHE_BUFFERABLE = UInt(1, width = cacheBits)
val PROT_PRIVILEDGED = UInt(1, width = protBits)
val PROT_INSECURE = UInt(2, width = protBits)
val PROT_INSTRUCTION = UInt(4, width = protBits)
def PROT_PRIVILEDGED = UInt(1, width = protBits)
def PROT_INSECURE = UInt(2, width = protBits)
def PROT_INSTRUCTION = UInt(4, width = protBits)
val BURST_FIXED = UInt(0, width = burstBits)
val BURST_INCR = UInt(1, width = burstBits)
val BURST_WRAP = UInt(2, width = burstBits)
def BURST_FIXED = UInt(0, width = burstBits)
def BURST_INCR = UInt(1, width = burstBits)
def BURST_WRAP = UInt(2, width = burstBits)
val RESP_OKAY = UInt(0, width = respBits)
val RESP_EXOKAY = UInt(1, width = respBits)
val RESP_SLVERR = UInt(2, width = respBits)
val RESP_DECERR = UInt(3, width = respBits)
def RESP_OKAY = UInt(0, width = respBits)
def RESP_EXOKAY = UInt(1, width = respBits)
def RESP_SLVERR = UInt(2, width = respBits)
def RESP_DECERR = UInt(3, width = respBits)
}

8
src/main/scala/uncore/tilelink2/Broadcast.scala
View File

@ -291,10 +291,10 @@ class TLBroadcastTracker(id: Int, lineBytes: Int, probeCountBits: Int, bufferles
object TLBroadcastConstants
{
val TRANSFORM_T = UInt(3)
val TRANSFORM_B = UInt(2)
val DROP = UInt(1)
val PASS = UInt(0)
def TRANSFORM_T = UInt(3)
def TRANSFORM_B = UInt(2)
def DROP = UInt(1)
def PASS = UInt(0)
}
class TLBroadcastData(params: TLBundleParameters) extends TLBundleBase(params)

84
src/main/scala/uncore/tilelink2/Bundles.scala
View File

@ -16,25 +16,25 @@ abstract class TLBundleBase(params: TLBundleParameters) extends GenericParameter
object TLMessages
{
// A B C D E
val PutFullData = UInt(0) // . . => AccessAck
val PutPartialData = UInt(1) // . . => AccessAck
val ArithmeticData = UInt(2) // . . => AccessAckData
val LogicalData = UInt(3) // . . => AccessAckData
val Get = UInt(4) // . . => AccessAckData
val Hint = UInt(5) // . . => HintAck
val Acquire = UInt(6) // . => Grant[Data]
val Probe = UInt(6) // . => ProbeAck[Data]
val AccessAck = UInt(0) // . .
val AccessAckData = UInt(1) // . .
val HintAck = UInt(2) // . .
val ProbeAck = UInt(4) // .
val ProbeAckData = UInt(5) // .
val Release = UInt(6) // . => ReleaseAck
val ReleaseData = UInt(7) // . => ReleaseAck
val Grant = UInt(4) // . => GrantAck
val GrantData = UInt(5) // . => GrantAck
val ReleaseAck = UInt(6) // .
val GrantAck = UInt(0) // .
def PutFullData = UInt(0) // . . => AccessAck
def PutPartialData = UInt(1) // . . => AccessAck
def ArithmeticData = UInt(2) // . . => AccessAckData
def LogicalData = UInt(3) // . . => AccessAckData
def Get = UInt(4) // . . => AccessAckData
def Hint = UInt(5) // . . => HintAck
def Acquire = UInt(6) // . => Grant[Data]
def Probe = UInt(6) // . => ProbeAck[Data]
def AccessAck = UInt(0) // . .
def AccessAckData = UInt(1) // . .
def HintAck = UInt(2) // . .
def ProbeAck = UInt(4) // .
def ProbeAckData = UInt(5) // .
def Release = UInt(6) // . => ReleaseAck
def ReleaseData = UInt(7) // . => ReleaseAck
def Grant = UInt(4) // . => GrantAck
def GrantData = UInt(5) // . => GrantAck
def ReleaseAck = UInt(6) // .
def GrantAck = UInt(0) // .
def isA(x: UInt) = x <= Acquire
def isB(x: UInt) = x <= Probe
@ -58,27 +58,27 @@ object TLPermissions
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
val toT = UInt(0, bdWidth)
val toB = UInt(1, bdWidth)
val toN = UInt(2, bdWidth)
def toT = UInt(0, bdWidth)
def toB = UInt(1, bdWidth)
def toN = UInt(2, bdWidth)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
val NtoB = UInt(0, aWidth)
val NtoT = UInt(1, aWidth)
val BtoT = UInt(2, aWidth)
def NtoB = UInt(0, aWidth)
def NtoT = UInt(1, aWidth)
def BtoT = UInt(2, aWidth)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
val TtoB = UInt(0, cWidth)
val TtoN = UInt(1, cWidth)
val BtoN = UInt(2, cWidth)
def TtoB = UInt(0, cWidth)
def TtoN = UInt(1, cWidth)
def BtoN = UInt(2, cWidth)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck)
val TtoT = UInt(3, cWidth)
val BtoB = UInt(4, cWidth)
val NtoN = UInt(5, cWidth)
def TtoT = UInt(3, cWidth)
def BtoB = UInt(4, cWidth)
def NtoN = UInt(5, cWidth)
def isReport(x: UInt) = x <= NtoN
}
@ -87,18 +87,18 @@ object TLAtomics
val width = 3
// Arithmetic types
val MIN = UInt(0, width)
val MAX = UInt(1, width)
val MINU = UInt(2, width)
val MAXU = UInt(3, width)
val ADD = UInt(4, width)
def MIN = UInt(0, width)
def MAX = UInt(1, width)
def MINU = UInt(2, width)
def MAXU = UInt(3, width)
def ADD = UInt(4, width)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
val XOR = UInt(0, width)
val OR = UInt(1, width)
val AND = UInt(2, width)
val SWAP = UInt(3, width)
def XOR = UInt(0, width)
def OR = UInt(1, width)
def AND = UInt(2, width)
def SWAP = UInt(3, width)
def isLogical(x: UInt) = x <= SWAP
}
@ -106,8 +106,8 @@ object TLHints
{
val width = 1
val PREFETCH_READ = UInt(0, width)
val PREFETCH_WRITE = UInt(1, width)
def PREFETCH_READ = UInt(0, width)
def PREFETCH_WRITE = UInt(1, width)
}
sealed trait TLChannel extends TLBundleBase {

8
src/main/scala/uncore/tilelink2/Metadata.scala
View File

@ -11,10 +11,10 @@ import uncore.constants.MemoryOpConstants
object ClientStates {
val width = 2
val Nothing = UInt(0, width)
val Branch = UInt(1, width)
val Trunk = UInt(2, width)
val Dirty = UInt(3, width)
def Nothing = UInt(0, width)
def Branch = UInt(1, width)
def Trunk = UInt(2, width)
def Dirty = UInt(3, width)
def hasReadPermission(state: UInt): Bool = state > Nothing
def hasWritePermission(state: UInt): Bool = state > Branch