riscv/rocket-chip
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rocketchip: work-around ucb-bar/chisel3#472

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This commit is contained in:
Wesley W. Terpstra
2017-01-31 13:54:02 -08:00
parent 9c0cc6fdf4
commit e5af59db68
14 changed files with 223 additions and 223 deletions
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36
src/main/scala/rocket/FPU.scala
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@ -19,24 +19,24 @@ case class FPUConfig(
object FPConstants
{
val FCMD_ADD = BitPat("b0??00")
val FCMD_SUB = BitPat("b0??01")
val FCMD_MUL = BitPat("b0??10")
val FCMD_MADD = BitPat("b1??00")
val FCMD_MSUB = BitPat("b1??01")
val FCMD_NMSUB = BitPat("b1??10")
val FCMD_NMADD = BitPat("b1??11")
val FCMD_DIV = BitPat("b?0011")
val FCMD_SQRT = BitPat("b?1011")
val FCMD_SGNJ = BitPat("b??1?0")
val FCMD_MINMAX = BitPat("b?01?1")
val FCMD_CVT_FF = BitPat("b??0??")
val FCMD_CVT_IF = BitPat("b?10??")
val FCMD_CMP = BitPat("b?01??")
val FCMD_MV_XF = BitPat("b?11??")
val FCMD_CVT_FI = BitPat("b??0??")
val FCMD_MV_FX = BitPat("b??1??")
val FCMD_X = BitPat("b?????")
def FCMD_ADD = BitPat("b0??00")
def FCMD_SUB = BitPat("b0??01")
def FCMD_MUL = BitPat("b0??10")
def FCMD_MADD = BitPat("b1??00")
def FCMD_MSUB = BitPat("b1??01")
def FCMD_NMSUB = BitPat("b1??10")
def FCMD_NMADD = BitPat("b1??11")
def FCMD_DIV = BitPat("b?0011")
def FCMD_SQRT = BitPat("b?1011")
def FCMD_SGNJ = BitPat("b??1?0")
def FCMD_MINMAX = BitPat("b?01?1")
def FCMD_CVT_FF = BitPat("b??0??")
def FCMD_CVT_IF = BitPat("b?10??")
def FCMD_CMP = BitPat("b?01??")
def FCMD_MV_XF = BitPat("b?11??")
def FCMD_CVT_FI = BitPat("b??0??")
def FCMD_MV_FX = BitPat("b??1??")
def FCMD_X = BitPat("b?????")
val FCMD_WIDTH = 5
val RM_SZ = 3

10
src/main/scala/rocket/Rocc.scala
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@ -407,11 +407,11 @@ class OpcodeSet(val opcodes: Seq[UInt]) {
}
object OpcodeSet {
val custom0 = new OpcodeSet(Seq(Bits("b0001011")))
val custom1 = new OpcodeSet(Seq(Bits("b0101011")))
val custom2 = new OpcodeSet(Seq(Bits("b1011011")))
val custom3 = new OpcodeSet(Seq(Bits("b1111011")))
val all = custom0 | custom1 | custom2 | custom3
def custom0 = new OpcodeSet(Seq(Bits("b0001011")))
def custom1 = new OpcodeSet(Seq(Bits("b0101011")))
def custom2 = new OpcodeSet(Seq(Bits("b1011011")))
def custom3 = new OpcodeSet(Seq(Bits("b1111011")))
def all = custom0 | custom1 | custom2 | custom3
}
class RoccCommandRouter(opcodes: Seq[OpcodeSet])(implicit p: Parameters)

80
src/main/scala/rocket/consts.scala
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@ -8,54 +8,54 @@ import scala.math._
trait ScalarOpConstants {
val MT_SZ = 3
val MT_X = BitPat("b???")
val MT_B = UInt("b000")
val MT_H = UInt("b001")
val MT_W = UInt("b010")
val MT_D = UInt("b011")
val MT_BU = UInt("b100")
val MT_HU = UInt("b101")
val MT_WU = UInt("b110")
def MT_X = BitPat("b???")
def MT_B = UInt("b000")
def MT_H = UInt("b001")
def MT_W = UInt("b010")
def MT_D = UInt("b011")
def MT_BU = UInt("b100")
def MT_HU = UInt("b101")
def MT_WU = UInt("b110")
def mtSize(mt: UInt) = mt(MT_SZ-2, 0)
def mtSigned(mt: UInt) = !mt(MT_SZ-1)
val SZ_BR = 3
val BR_X = BitPat("b???")
val BR_EQ = UInt(0, 3)
val BR_NE = UInt(1, 3)
val BR_J = UInt(2, 3)
val BR_N = UInt(3, 3)
val BR_LT = UInt(4, 3)
val BR_GE = UInt(5, 3)
val BR_LTU = UInt(6, 3)
val BR_GEU = UInt(7, 3)
def BR_X = BitPat("b???")
def BR_EQ = UInt(0, 3)
def BR_NE = UInt(1, 3)
def BR_J = UInt(2, 3)
def BR_N = UInt(3, 3)
def BR_LT = UInt(4, 3)
def BR_GE = UInt(5, 3)
def BR_LTU = UInt(6, 3)
def BR_GEU = UInt(7, 3)
val A1_X = BitPat("b??")
val A1_ZERO = UInt(0, 2)
val A1_RS1 = UInt(1, 2)
val A1_PC = UInt(2, 2)
def A1_X = BitPat("b??")
def A1_ZERO = UInt(0, 2)
def A1_RS1 = UInt(1, 2)
def A1_PC = UInt(2, 2)
val IMM_X = BitPat("b???")
val IMM_S = UInt(0, 3)
val IMM_SB = UInt(1, 3)
val IMM_U = UInt(2, 3)
val IMM_UJ = UInt(3, 3)
val IMM_I = UInt(4, 3)
val IMM_Z = UInt(5, 3)
def IMM_X = BitPat("b???")
def IMM_S = UInt(0, 3)
def IMM_SB = UInt(1, 3)
def IMM_U = UInt(2, 3)
def IMM_UJ = UInt(3, 3)
def IMM_I = UInt(4, 3)
def IMM_Z = UInt(5, 3)
val A2_X = BitPat("b??")
val A2_ZERO = UInt(0, 2)
val A2_SIZE = UInt(1, 2)
val A2_RS2 = UInt(2, 2)
val A2_IMM = UInt(3, 2)
def A2_X = BitPat("b??")
def A2_ZERO = UInt(0, 2)
def A2_SIZE = UInt(1, 2)
def A2_RS2 = UInt(2, 2)
def A2_IMM = UInt(3, 2)
val X = BitPat("b?")
val N = BitPat("b0")
val Y = BitPat("b1")
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
val DW_X = X
val DW_32 = Bool(false)
val DW_64 = Bool(true)
val DW_XPR = DW_64
def DW_X = X
def DW_32 = Bool(false)
def DW_64 = Bool(true)
def DW_XPR = DW_64
}

14
src/main/scala/rocket/csr.scala
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@ -103,13 +103,13 @@ object CSR
{
// commands
val SZ = 3
val X = BitPat.dontCare(SZ)
val N = UInt(0,SZ)
val W = UInt(1,SZ)
val S = UInt(2,SZ)
val C = UInt(3,SZ)
val I = UInt(4,SZ)
val R = UInt(5,SZ)
def X = BitPat.dontCare(SZ)
def N = UInt(0,SZ)
def W = UInt(1,SZ)
def S = UInt(2,SZ)
def C = UInt(3,SZ)
def I = UInt(4,SZ)
def R = UInt(5,SZ)
val ADDRSZ = 12
val debugIntCause = new MIP().getWidth

46
src/main/scala/rocket/dpath_alu.scala
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@ -10,31 +10,31 @@ import Instructions._
object ALU
{
val SZ_ALU_FN = 4
val FN_X = BitPat("b????")
val FN_ADD = UInt(0)
val FN_SL = UInt(1)
val FN_SEQ = UInt(2)
val FN_SNE = UInt(3)
val FN_XOR = UInt(4)
val FN_SR = UInt(5)
val FN_OR = UInt(6)
val FN_AND = UInt(7)
val FN_SUB = UInt(10)
val FN_SRA = UInt(11)
val FN_SLT = UInt(12)
val FN_SGE = UInt(13)
val FN_SLTU = UInt(14)
val FN_SGEU = UInt(15)
def FN_X = BitPat("b????")
def FN_ADD = UInt(0)
def FN_SL = UInt(1)
def FN_SEQ = UInt(2)
def FN_SNE = UInt(3)
def FN_XOR = UInt(4)
def FN_SR = UInt(5)
def FN_OR = UInt(6)
def FN_AND = UInt(7)
def FN_SUB = UInt(10)
def FN_SRA = UInt(11)
def FN_SLT = UInt(12)
def FN_SGE = UInt(13)
def FN_SLTU = UInt(14)
def FN_SGEU = UInt(15)
val FN_DIV = FN_XOR
val FN_DIVU = FN_SR
val FN_REM = FN_OR
val FN_REMU = FN_AND
def FN_DIV = FN_XOR
def FN_DIVU = FN_SR
def FN_REM = FN_OR
def FN_REMU = FN_AND
val FN_MUL = FN_ADD
val FN_MULH = FN_SL
val FN_MULHSU = FN_SLT
val FN_MULHU = FN_SLTU
def FN_MUL = FN_ADD
def FN_MULH = FN_SL
def FN_MULHSU = FN_SLT
def FN_MULHU = FN_SLTU
def isMulFN(fn: UInt, cmp: UInt) = fn(1,0) === cmp(1,0)
def isSub(cmd: UInt) = cmd(3)