rocketchip: work-around ucb-bar/chisel3#472

src/main/scala/junctions/hasti.scala

@@ -12,26 +12,26 @@ object HastiConstants
 {
   // Values for htrans
   val SZ_HTRANS     = 2
-  val HTRANS_IDLE   = UInt(0, SZ_HTRANS) // No transfer requested, not in a burst
-  val HTRANS_BUSY   = UInt(1, SZ_HTRANS) // No transfer requested, in a burst
-  val HTRANS_NONSEQ = UInt(2, SZ_HTRANS) // First (potentially only) request in a burst
-  val HTRANS_SEQ    = UInt(3, SZ_HTRANS) // Following requests in a burst
+  def HTRANS_IDLE   = UInt(0, SZ_HTRANS) // No transfer requested, not in a burst
+  def HTRANS_BUSY   = UInt(1, SZ_HTRANS) // No transfer requested, in a burst
+  def HTRANS_NONSEQ = UInt(2, SZ_HTRANS) // First (potentially only) request in a burst
+  def HTRANS_SEQ    = UInt(3, SZ_HTRANS) // Following requests in a burst
 
   // Values for hburst
   val SZ_HBURST     = 3
-  val HBURST_SINGLE = UInt(0, SZ_HBURST) // Single access (no burst)
-  val HBURST_INCR   = UInt(1, SZ_HBURST) // Incrementing burst of arbitrary length, not crossing 1KB
-  val HBURST_WRAP4  = UInt(2, SZ_HBURST) // 4-beat wrapping burst
-  val HBURST_INCR4  = UInt(3, SZ_HBURST) // 4-beat incrementing burst
-  val HBURST_WRAP8  = UInt(4, SZ_HBURST) // 8-beat wrapping burst
-  val HBURST_INCR8  = UInt(5, SZ_HBURST) // 8-beat incrementing burst
-  val HBURST_WRAP16 = UInt(6, SZ_HBURST) // 16-beat wrapping burst
-  val HBURST_INCR16 = UInt(7, SZ_HBURST) // 16-beat incrementing burst
+  def HBURST_SINGLE = UInt(0, SZ_HBURST) // Single access (no burst)
+  def HBURST_INCR   = UInt(1, SZ_HBURST) // Incrementing burst of arbitrary length, not crossing 1KB
+  def HBURST_WRAP4  = UInt(2, SZ_HBURST) // 4-beat wrapping burst
+  def HBURST_INCR4  = UInt(3, SZ_HBURST) // 4-beat incrementing burst
+  def HBURST_WRAP8  = UInt(4, SZ_HBURST) // 8-beat wrapping burst
+  def HBURST_INCR8  = UInt(5, SZ_HBURST) // 8-beat incrementing burst
+  def HBURST_WRAP16 = UInt(6, SZ_HBURST) // 16-beat wrapping burst
+  def HBURST_INCR16 = UInt(7, SZ_HBURST) // 16-beat incrementing burst
 
   // Values for hresp
   val SZ_HRESP      = 1
-  val HRESP_OKAY    = UInt(0, SZ_HRESP)
-  val HRESP_ERROR   = UInt(1, SZ_HRESP)
+  def HRESP_OKAY    = UInt(0, SZ_HRESP)
+  def HRESP_ERROR   = UInt(1, SZ_HRESP)
 
   // Values for hsize are identical to TileLink MT_SZ
   // ie: 8*2^SZ_HSIZE bit transfers

src/main/scala/junctions/nasti.scala

@@ -128,19 +128,19 @@ class NastiReadDataChannel(implicit p: Parameters) extends NastiResponseChannel(
 }
 
 object NastiConstants {
-  val BURST_FIXED = UInt("b00")
-  val BURST_INCR  = UInt("b01")
-  val BURST_WRAP  = UInt("b10")
+  def BURST_FIXED = UInt("b00")
+  def BURST_INCR  = UInt("b01")
+  def BURST_WRAP  = UInt("b10")
 
-  val RESP_OKAY = UInt("b00")
-  val RESP_EXOKAY = UInt("b01")
-  val RESP_SLVERR = UInt("b10")
-  val RESP_DECERR = UInt("b11")
+  def RESP_OKAY = UInt("b00")
+  def RESP_EXOKAY = UInt("b01")
+  def RESP_SLVERR = UInt("b10")
+  def RESP_DECERR = UInt("b11")
 
-  val CACHE_DEVICE_NOBUF = UInt("b0000")
-  val CACHE_DEVICE_BUF   = UInt("b0001")
-  val CACHE_NORMAL_NOCACHE_NOBUF = UInt("b0010")
-  val CACHE_NORMAL_NOCACHE_BUF   = UInt("b0011")
+  def CACHE_DEVICE_NOBUF = UInt("b0000")
+  def CACHE_DEVICE_BUF   = UInt("b0001")
+  def CACHE_NORMAL_NOCACHE_NOBUF = UInt("b0010")
+  def CACHE_NORMAL_NOCACHE_BUF   = UInt("b0011")
 
   def AXPROT(instruction: Bool, nonsecure: Bool, privileged: Bool): UInt =
     Cat(instruction, nonsecure, privileged)