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tilelink2 Fragmenter: eliminate most of the registers on A

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This commit is contained in:
Wesley W. Terpstra 2016-10-12 20:27:26 -07:00
parent 99c7003d11
commit e5a1483358
2 changed files with 14 additions and 4 deletions
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16
src/main/scala/uncore/tilelink2/Fragmenter.scala
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@ -190,9 +190,10 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m))) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m))) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
// Make the request Irrevocable // Make the request repeatable
val repeat = Wire(Bool()) val repeater = Module(new Repeater(in.a.bits))
val in_a = Repeater(in.a, repeat) repeater.io.enq <> in.a
val in_a = repeater.io.deq
// If this is infront of a single manager, these become constants // If this is infront of a single manager, these become constants
val find = manager.findFast(edgeIn.address(in_a.bits)) val find = manager.findFast(edgeIn.address(in_a.bits))
@ -227,12 +228,19 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
when (out.a.fire()) { gennum := new_gennum } when (out.a.fire()) { gennum := new_gennum }
repeat := !aHasData && aFragnum =/= UInt(0) repeater.io.repeat := !aHasData && aFragnum =/= UInt(0)
out.a <> in_a out.a <> in_a
out.a.bits.addr_hi := in_a.bits.addr_hi | (~aFragnum << log2Ceil(minSize/beatBytes) & aOrigOH1 >> log2Ceil(beatBytes)) out.a.bits.addr_hi := in_a.bits.addr_hi | (~aFragnum << log2Ceil(minSize/beatBytes) & aOrigOH1 >> log2Ceil(beatBytes))
out.a.bits.source := Cat(in_a.bits.source, aFragnum) out.a.bits.source := Cat(in_a.bits.source, aFragnum)
out.a.bits.size := aFrag out.a.bits.size := aFrag
// Optimize away some of the Repeater's registers
assert (!repeater.io.full || !aHasData)
out.a.bits.data := in.a.bits.data
val fullMask = UInt((BigInt(1) << beatBytes) - 1)
assert (!repeater.io.full || in_a.bits.mask === fullMask)
out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
// Tie off unused channels // Tie off unused channels
in.b.valid := Bool(false) in.b.valid := Bool(false)
in.c.ready := Bool(true) in.c.ready := Bool(true)

2
src/main/scala/uncore/tilelink2/Repeater.scala
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@ -10,6 +10,7 @@ class Repeater[T <: Data](gen: T) extends Module
{ {
val io = new Bundle { val io = new Bundle {
val repeat = Bool(INPUT) val repeat = Bool(INPUT)
val full = Bool(OUTPUT)
val enq = Decoupled(gen).flip val enq = Decoupled(gen).flip
val deq = Decoupled(gen) val deq = Decoupled(gen)
} }
@ -21,6 +22,7 @@ class Repeater[T <: Data](gen: T) extends Module
io.deq.valid := io.enq.valid || full io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits) io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire() && io.repeat) { full := Bool(true); saved := io.enq.bits } when (io.enq.fire() && io.repeat) { full := Bool(true); saved := io.enq.bits }
when (io.deq.fire() && !io.repeat) { full := Bool(false) } when (io.deq.fire() && !io.repeat) { full := Bool(false) }