Merge branch 'master' into hwacha

project/build.scala

@@ -13,6 +13,7 @@ object BuildSettings extends Build {
     organization := buildOrganization,
     version      := buildVersion,
     scalaVersion := buildScalaVersion,
+    parallelExecution in Global := false,
     traceLevel   := 15,
     scalacOptions ++= Seq("-deprecation","-unchecked"),
     libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value)

riscv-tools

@@ -1 +1 @@
-Subproject commit e6286fa57d70f1a90711f4dabe2a3f914555ff46
+Subproject commit 17a9427f93b7319c5e27051bbd6d4d3b8026f70c

rocket

@@ -1 +1 @@
-Subproject commit 02da61cc09e674ca9a5f9baaeac580d30cf7d693
+Subproject commit 2728029ceb287ac528428ed0f726c193ffcc4133

src/main/scala/RocketChip.scala

@@ -157,7 +157,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
     val mem_backup = new ioMemSerialized(htif_width)
     val mem_backup_en = Bool(INPUT)
   }
-  val htif = Module(new RocketHTIF(htif_width, conf.nSCR))
+  val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR))
   val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif))
   val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
   outmemsys.io.incoherent := incoherentWithHtif

src/main/scala/fpga.scala

@@ -45,7 +45,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
     val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
     val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
   }
-  val htif = Module(new RocketHTIF(htif_width, conf.nSCR))
+  val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR))
   val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif))
   val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
   outmemsys.io.incoherent := incoherentWithHtif

uncore

@@ -1 +1 @@
-Subproject commit c0d3194ff8850a90b0d43c92c5e99e77a779f7c8
+Subproject commit 9eadc3d8c87507fbc8981d3ff9a7490ab8a35851