From ad1d8f219e00668fd320c5d6916613462398794d Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 5 Nov 2013 21:10:49 -0800 Subject: [PATCH 1/4] push riscv-tools --- riscv-tools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-tools b/riscv-tools index e6286fa5..17a9427f 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit e6286fa57d70f1a90711f4dabe2a3f914555ff46 +Subproject commit 17a9427f93b7319c5e27051bbd6d4d3b8026f70c From 1d6d4b4e96a174548698c0e9aeabcabbba97cde2 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 7 Nov 2013 13:19:19 -0800 Subject: [PATCH 2/4] move htif to uncore --- rocket | 2 +- src/main/scala/RocketChip.scala | 2 +- src/main/scala/fpga.scala | 2 +- uncore | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/rocket b/rocket index b1012b25..f015a75d 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit b1012b251061631fe00bcdd5327a1e2fba1e6f61 +Subproject commit f015a75dd39cc5dae2aafeb23715273a5b5a614a diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index d282d2b0..b1df61c0 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -157,7 +157,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf val mem_backup = new ioMemSerialized(htif_width) val mem_backup_en = Bool(INPUT) } - val htif = Module(new RocketHTIF(htif_width, conf.nSCR)) + val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR)) val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 9c880e24..3aab9d29 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -45,7 +45,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput } - val htif = Module(new RocketHTIF(htif_width, conf.nSCR)) + val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR)) val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif diff --git a/uncore b/uncore index c0d3194f..df449873 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit c0d3194ff8850a90b0d43c92c5e99e77a779f7c8 +Subproject commit df449873bef7a5b657895e5e43b4f5b3941f549e From bb64c900928039972d9d79597150a109050dbb9a Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 7 Nov 2013 15:42:21 -0800 Subject: [PATCH 3/4] forgot to put htif into uncore package --- rocket | 2 +- uncore | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket b/rocket index f015a75d..bad7213d 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit f015a75dd39cc5dae2aafeb23715273a5b5a614a +Subproject commit bad7213d9dcb064fb1fe53395fdcd47092fb9e96 diff --git a/uncore b/uncore index df449873..9eadc3d8 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit df449873bef7a5b657895e5e43b4f5b3941f549e +Subproject commit 9eadc3d8c87507fbc8981d3ff9a7490ab8a35851 From c137cf1a46a6b2311a451259b4d570ba6308dcc1 Mon Sep 17 00:00:00 2001 From: Ben Keller Date: Fri, 8 Nov 2013 15:30:08 -0800 Subject: [PATCH 4/4] Added line to fix race condition in sbt compile; fixed .gitignores --- project/build.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/project/build.scala b/project/build.scala index 5bf99b3c..e952ac76 100644 --- a/project/build.scala +++ b/project/build.scala @@ -13,6 +13,7 @@ object BuildSettings extends Build { organization := buildOrganization, version := buildVersion, scalaVersion := buildScalaVersion, + parallelExecution in Global := false, traceLevel := 15, scalacOptions ++= Seq("-deprecation","-unchecked"), libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value)