riscv/rocket-chip
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Merge branch 'master' into hwacha

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This commit is contained in:
Stephen Twigg 2013-11-14 16:03:55 -08:00
commit e50c5180cd
6 changed files with 6 additions and 5 deletions
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1
project/build.scala
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@ -13,6 +13,7 @@ object BuildSettings extends Build {
organization := buildOrganization, organization := buildOrganization,
version := buildVersion, version := buildVersion,
scalaVersion := buildScalaVersion, scalaVersion := buildScalaVersion,
parallelExecution in Global := false,
traceLevel := 15, traceLevel := 15,
scalacOptions ++= Seq("-deprecation","-unchecked"), scalacOptions ++= Seq("-deprecation","-unchecked"),
libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value) libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value)

2
riscv-tools

@ -1 +1 @@
Subproject commit e6286fa57d70f1a90711f4dabe2a3f914555ff46 Subproject commit 17a9427f93b7319c5e27051bbd6d4d3b8026f70c

2
rocket

@ -1 +1 @@
Subproject commit 02da61cc09e674ca9a5f9baaeac580d30cf7d693 Subproject commit 2728029ceb287ac528428ed0f726c193ffcc4133

2
src/main/scala/RocketChip.scala
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@ -157,7 +157,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
val mem_backup = new ioMemSerialized(htif_width) val mem_backup = new ioMemSerialized(htif_width)
val mem_backup_en = Bool(INPUT) val mem_backup_en = Bool(INPUT)
} }
val htif = Module(new RocketHTIF(htif_width, conf.nSCR)) val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR))
val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif)) val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif outmemsys.io.incoherent := incoherentWithHtif

2
src/main/scala/fpga.scala
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@ -45,7 +45,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
} }
val htif = Module(new RocketHTIF(htif_width, conf.nSCR)) val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR))
val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif)) val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif outmemsys.io.incoherent := incoherentWithHtif

2
uncore

@ -1 +1 @@
Subproject commit c0d3194ff8850a90b0d43c92c5e99e77a779f7c8 Subproject commit 9eadc3d8c87507fbc8981d3ff9a7490ab8a35851