riscv/rocket-chip
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generate verilog for rekall

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Yunsup Lee 2014-03-15 15:31:04 -07:00
parent b6bf7cfe0c
commit e4b56b5d0e
1 changed files with 2 additions and 1 deletions
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project/build.scala
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@ -31,7 +31,8 @@ object BuildSettings extends Build {
lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat)
lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore)
lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket)
lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha)
lazy val rekall = Project("rekall", file("rekall"), settings = buildSettings) dependsOn(chisel)
lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha, rekall)
val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")