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diplomacy: remove node arity and allow empty Nexus nodes (Xbars)

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This removes the mostly obsolete 'numIn/Out' range restrictions on nodes.
It also makes it possible to connect optional crossbars that disappear.

val x = TLXbar()
x := master
slave := x

val y = TLXbar()
x :=* y // only connect y if it gets used

This will create crossbar x, but crossbar y will disappear.
This commit is contained in:
Wesley W. Terpstra
2017-11-30 14:43:43 -08:00
parent 6a25a3b7ac
commit e489c4226e
16 changed files with 155 additions and 182 deletions
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19
src/main/scala/devices/tilelink/BusBypass.scala
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@ -37,14 +37,21 @@ class TLBusBypass(beatBytes: Int)(implicit p: Parameters) extends TLBusBypassBas
}
}
class TLBypassNode(implicit valName: ValName) extends TLCustomNode
{
def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
require (iStars == 0 && oStars == 0, "TLBypass node does not support :=* or :*=")
require (iKnown == 1, "TLBypass node expects exactly one input")
require (oKnown == 2, "TLBypass node expects exactly one output")
(0, 0)
}
def mapParamsD(n: Int, p: Seq[TLClientPortParameters]): Seq[TLClientPortParameters] = { p ++ p }
def mapParamsU(n: Int, p: Seq[TLManagerPortParameters]): Seq[TLManagerPortParameters] = { p.tail }
}
class TLBusBypassBar(implicit p: Parameters) extends LazyModule
{
// The client only sees the second slave port
val node = TLNexusNode(
numClientPorts = 2 to 2 ,
numManagerPorts = 1 to 1,
clientFn = { seq => seq(0) },
managerFn = { seq => seq(1) })
val node = new TLBypassNode()
lazy val module = new LazyModuleImp(this) {
val io = IO(new Bundle {

9
src/main/scala/devices/tilelink/Clint.scala
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@ -48,12 +48,13 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
beatBytes = p(XLen)/8)
val intnode = IntNexusNode(
numSourcePorts = 0 to 1024,
numSinkPorts = 0 to 0,
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false)
lazy val module = new LazyModuleImp(this) {
require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them")
val io = IO(new Bundle {
val rtcTick = Bool(INPUT)
})

8
src/main/scala/devices/tilelink/Plic.scala
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@ -86,10 +86,10 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
concurrency = 1) // limiting concurrency handles RAW hazards on claim registers
val intnode = IntNexusNode(
numSourcePorts = 0 to 1024,
numSinkPorts = 0 to 1024,
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false,
inputRequiresOutput = false)
/* Negotiated sizes */
def nDevices: Int = intnode.edges.in.map(_.source.num).sum