riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

diplomacy: remove node arity and allow empty Nexus nodes (Xbars)

Browse Source 
This removes the mostly obsolete 'numIn/Out' range restrictions on nodes.
It also makes it possible to connect optional crossbars that disappear.

val x = TLXbar()
x := master
slave := x

val y = TLXbar()
x :=* y // only connect y if it gets used

This will create crossbar x, but crossbar y will disappear.
This commit is contained in:
Wesley W. Terpstra
2017-11-30 14:43:43 -08:00
parent 6a25a3b7ac
commit e489c4226e
16 changed files with 155 additions and 182 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/amba/ahb/Nodes.scala
View File

@ -24,10 +24,8 @@ case class AHBMasterNode(portParams: Seq[AHBMasterPortParameters])(implicit valN
case class AHBSlaveNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends SinkNode(AHBImp)(portParams)
case class AHBNexusNode(
masterFn: Seq[AHBMasterPortParameters] => AHBMasterPortParameters,
slaveFn: Seq[AHBSlavePortParameters] => AHBSlavePortParameters,
numMasterPorts: Range.Inclusive = 1 to 999,
numSlavePorts: Range.Inclusive = 1 to 999)(
slaveFn: Seq[AHBSlavePortParameters] => AHBSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(AHBImp)(masterFn, slaveFn, numMasterPorts, numSlavePorts)
extends NexusNode(AHBImp)(masterFn, slaveFn)
case class AHBIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImp)()

57
src/main/scala/amba/ahb/Xbar.scala
View File

@ -10,37 +10,40 @@ import scala.math.{min,max}
class AHBFanout()(implicit p: Parameters) extends LazyModule {
val node = AHBNexusNode(
numSlavePorts = 1 to 1,
numMasterPorts = 1 to 32,
masterFn = { case Seq(m) => m },
slaveFn = { seq => seq(0).copy(slaves = seq.flatMap(_.slaves)) })
lazy val module = new LazyModuleImp(this) {
// Require consistent bus widths
val (io_out, edgesOut) = node.out.unzip
val port0 = edgesOut(0).slave
edgesOut.foreach { edge =>
val port = edge.slave
require (port.beatBytes == port0.beatBytes,
s"${port.slaves.map(_.name)} ${port.beatBytes} vs ${port0.slaves.map(_.name)} ${port0.beatBytes}")
if (node.edges.in.size >= 1) {
require (node.edges.in.size == 1, "AHBFanout does not support multiple masters")
require (node.edges.out.size > 0, "AHBFanout requires at least one slave")
// Require consistent bus widths
val (io_out, edgesOut) = node.out.unzip
val port0 = edgesOut(0).slave
edgesOut.foreach { edge =>
val port = edge.slave
require (port.beatBytes == port0.beatBytes,
s"${port.slaves.map(_.name)} ${port.beatBytes} vs ${port0.slaves.map(_.name)} ${port0.beatBytes}")
}
val port_addrs = edgesOut.map(_.slave.slaves.map(_.address).flatten)
val routingMask = AddressDecoder(port_addrs)
val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct)
val (in, _) = node.in(0)
val a_sel = Vec(route_addrs.map(seq => seq.map(_.contains(in.haddr)).reduce(_ || _)))
val d_sel = Reg(a_sel)
when (in.hready) { d_sel := a_sel }
(a_sel zip io_out) foreach { case (sel, out) =>
out := in
out.hsel := in.hsel && sel
}
in.hreadyout := !Mux1H(d_sel, io_out.map(!_.hreadyout))
in.hresp := Mux1H(d_sel, io_out.map(_.hresp))
in.hrdata := Mux1H(d_sel, io_out.map(_.hrdata))
}
val port_addrs = edgesOut.map(_.slave.slaves.map(_.address).flatten)
val routingMask = AddressDecoder(port_addrs)
val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct)
val (in, _) = node.in(0)
val a_sel = Vec(route_addrs.map(seq => seq.map(_.contains(in.haddr)).reduce(_ || _)))
val d_sel = Reg(a_sel)
when (in.hready) { d_sel := a_sel }
(a_sel zip io_out) foreach { case (sel, out) =>
out := in
out.hsel := in.hsel && sel
}
in.hreadyout := !Mux1H(d_sel, io_out.map(!_.hreadyout))
in.hresp := Mux1H(d_sel, io_out.map(_.hresp))
in.hrdata := Mux1H(d_sel, io_out.map(_.hrdata))
}
}