riscv/rocket-chip
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Don't rely on SeqMem output after read-enable is low

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This commit is contained in:
Andrew Waterman 2016-10-27 23:44:10 -07:00
parent 190a8b9dd3
commit e45b41b4b6
2 changed files with 8 additions and 2 deletions
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6
src/main/scala/uncore/axi4/SRAM.scala
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@ -59,9 +59,13 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int =
r_id := in.ar.bits.id r_id := in.ar.bits.id
} }
val ren = in.ar.fire()
def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
val rdata = holdUnless(mem.read(r_addr, ren), RegNext(ren))
in.r.bits.id := r_id in.r.bits.id := r_id
in.r.bits.resp := AXI4Parameters.RESP_OKAY in.r.bits.resp := AXI4Parameters.RESP_OKAY
in.r.bits.data := Cat(mem.read(r_addr, in.ar.fire()).reverse) in.r.bits.data := Cat(rdata.reverse)
in.r.bits.last := Bool(true) in.r.bits.last := Bool(true)
} }
} }

4
src/main/scala/uncore/tilelink2/SRAM.scala
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@ -71,7 +71,9 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)
when (in.a.fire() && !read) { when (in.a.fire() && !read) {
mem.write(memAddress, wdata, in.a.bits.mask.toBools) mem.write(memAddress, wdata, in.a.bits.mask.toBools)
} }
rdata := mem.read(memAddress, in.a.fire() && read) val ren = in.a.fire() && read
def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
rdata := holdUnless(mem.read(memAddress, ren), RegNext(ren))
// Tie off unused channels // Tie off unused channels
in.b.valid := Bool(false) in.b.valid := Bool(false)