From e45b41b4b632548cdba33e60d17dc9085b4e8757 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 27 Oct 2016 23:44:10 -0700 Subject: [PATCH] Don't rely on SeqMem output after read-enable is low --- src/main/scala/uncore/axi4/SRAM.scala | 6 +++++- src/main/scala/uncore/tilelink2/SRAM.scala | 4 +++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/axi4/SRAM.scala b/src/main/scala/uncore/axi4/SRAM.scala index c2014f94..7d259a11 100644 --- a/src/main/scala/uncore/axi4/SRAM.scala +++ b/src/main/scala/uncore/axi4/SRAM.scala @@ -59,9 +59,13 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = r_id := in.ar.bits.id } + val ren = in.ar.fire() + def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in) + val rdata = holdUnless(mem.read(r_addr, ren), RegNext(ren)) + in.r.bits.id := r_id in.r.bits.resp := AXI4Parameters.RESP_OKAY - in.r.bits.data := Cat(mem.read(r_addr, in.ar.fire()).reverse) + in.r.bits.data := Cat(rdata.reverse) in.r.bits.last := Bool(true) } } diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala index ea04563a..bbfbf0f6 100644 --- a/src/main/scala/uncore/tilelink2/SRAM.scala +++ b/src/main/scala/uncore/tilelink2/SRAM.scala @@ -71,7 +71,9 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) when (in.a.fire() && !read) { mem.write(memAddress, wdata, in.a.bits.mask.toBools) } - rdata := mem.read(memAddress, in.a.fire() && read) + val ren = in.a.fire() && read + def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in) + rdata := holdUnless(mem.read(memAddress, ren), RegNext(ren)) // Tie off unused channels in.b.valid := Bool(false)