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PTW now does not require atomic memory operations, so take out the requirement (#767)

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Bug fix in CSR which manifest itself when compiling a config with no extension
This commit is contained in:
Jacob Chang 2017-05-26 13:11:15 -07:00 committed by GitHub
parent 618468a06b
commit e3e77d68e6
2 changed files with 1 additions and 3 deletions
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2
src/main/scala/rocket/CSR.scala
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@ -794,5 +794,5 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
} }
} }
def formEPC(x: UInt) = ~(~x | Cat(!reg_misa('c'-'a'), UInt(1))) def formEPC(x: UInt) = ~(~x | Cat(!reg_misa('c'-'a'), UInt(1)))
def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).reduce(_|_) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_)
} }

2
src/main/scala/rocket/PTW.scala
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@ -71,8 +71,6 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
val dpath = new DatapathPTWIO val dpath = new DatapathPTWIO
} }
require(usingAtomics, "PTW requires atomic memory operations")
val s_ready :: s_req :: s_wait1 :: s_wait2 :: Nil = Enum(UInt(), 4) val s_ready :: s_req :: s_wait1 :: s_wait2 :: Nil = Enum(UInt(), 4)
val state = Reg(init=s_ready) val state = Reg(init=s_ready)
val count = Reg(UInt(width = log2Up(pgLevels))) val count = Reg(UInt(width = log2Up(pgLevels)))