From e3e77d68e6b7affc24dca56622ab95b6b5abf55c Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Fri, 26 May 2017 13:11:15 -0700 Subject: [PATCH] PTW now does not require atomic memory operations, so take out the requirement (#767) Bug fix in CSR which manifest itself when compiling a config with no extension --- src/main/scala/rocket/CSR.scala | 2 +- src/main/scala/rocket/PTW.scala | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index ae5c1f04..a51fbdfc 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -794,5 +794,5 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param } } def formEPC(x: UInt) = ~(~x | Cat(!reg_misa('c'-'a'), UInt(1))) - def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).reduce(_|_) + def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_) } diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala index d6a5b4fc..37ec12f7 100644 --- a/src/main/scala/rocket/PTW.scala +++ b/src/main/scala/rocket/PTW.scala @@ -71,8 +71,6 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()( val dpath = new DatapathPTWIO } - require(usingAtomics, "PTW requires atomic memory operations") - val s_ready :: s_req :: s_wait1 :: s_wait2 :: Nil = Enum(UInt(), 4) val state = Reg(init=s_ready) val count = Reg(UInt(width = log2Up(pgLevels)))