Make BTB more complexity-effective
BTB entries reference a small number of unique pages, so we separate the storage of pages from indices. This makes much larger BTBs feasible. It's easy to exacerbate cycle time this way, so one-hot encoding is used as needed.
This commit is contained in:
Andrew Waterman
246
rocket/src/main/scala/csr.scala
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246
rocket/src/main/scala/csr.scala
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package rocket
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import Chisel._
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import Util._
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import Node._
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import uncore.HTIFIO
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import uncore.constants.AddressConstants._
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import scala.math._
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class Status extends Bundle {
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val ip = Bits(width = 8)
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val im = Bits(width = 8)
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val zero = Bits(width = 7)
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val er = Bool()
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val vm = Bool()
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val s64 = Bool()
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val u64 = Bool()
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val ef = Bool()
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val pei = Bool()
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val ei = Bool()
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val ps = Bool()
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val s = Bool()
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}
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object CSR
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{
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// commands
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val SZ = 2
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val X = Bits("b??", 2)
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val N = Bits(0,2)
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val W = Bits(1,2)
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val S = Bits(2,2)
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val C = Bits(3,2)
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}
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class CSRFile(implicit conf: RocketConfiguration) extends Module
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{
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val io = new Bundle {
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val host = new HTIFIO(conf.tl.ln.nClients)
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val rw = new Bundle {
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val addr = UInt(INPUT, 12)
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val cmd = Bits(INPUT, CSR.SZ)
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val rdata = Bits(OUTPUT, conf.xprlen)
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val wdata = Bits(INPUT, conf.xprlen)
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}
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val status = new Status().asOutput
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val ptbr = UInt(OUTPUT, PADDR_BITS)
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val evec = UInt(OUTPUT, VADDR_BITS+1)
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val exception = Bool(INPUT)
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val retire = UInt(INPUT, log2Up(1+conf.retireWidth))
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val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+conf.retireWidth)))
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val cause = UInt(INPUT, conf.xprlen)
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val badvaddr_wen = Bool(INPUT)
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val pc = UInt(INPUT, VADDR_BITS+1)
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val sret = Bool(INPUT)
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val fatc = Bool(OUTPUT)
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val replay = Bool(OUTPUT)
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val time = UInt(OUTPUT, conf.xprlen)
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val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
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val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
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val rocc = new RoCCInterface().flip
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}
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val reg_epc = Reg(Bits(width = VADDR_BITS+1))
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val reg_badvaddr = Reg(Bits(width = VADDR_BITS))
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val reg_evec = Reg(Bits(width = VADDR_BITS))
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val reg_compare = Reg(Bits(width = 32))
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val reg_cause = Reg(Bits(width = conf.xprlen))
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val reg_tohost = Reg(init=Bits(0, conf.xprlen))
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val reg_fromhost = Reg(init=Bits(0, conf.xprlen))
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val reg_sup0 = Reg(Bits(width = conf.xprlen))
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val reg_sup1 = Reg(Bits(width = conf.xprlen))
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val reg_ptbr = Reg(UInt(width = PADDR_BITS))
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val reg_stats = Reg(init=Bool(false))
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val reg_status = Reg(new Status) // reset down below
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val reg_time = WideCounter(conf.xprlen)
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val reg_instret = WideCounter(conf.xprlen, io.retire)
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val reg_uarch_counters = io.uarch_counters.map(WideCounter(conf.xprlen, _))
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val reg_fflags = Reg(UInt(width = 5))
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val reg_frm = Reg(UInt(width = 3))
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val r_irq_timer = Reg(init=Bool(false))
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val r_irq_ipi = Reg(init=Bool(true))
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val irq_rocc = Bool(!conf.rocc.isEmpty) && io.rocc.interrupt
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val cpu_req_valid = io.rw.cmd != CSR.N
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val host_pcr_req_valid = Reg(Bool()) // don't reset
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val host_pcr_req_fire = host_pcr_req_valid && !cpu_req_valid
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val host_pcr_rep_valid = Reg(Bool()) // don't reset
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val host_pcr_bits = Reg(io.host.pcr_req.bits)
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io.host.pcr_req.ready := !host_pcr_req_valid && !host_pcr_rep_valid
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io.host.pcr_rep.valid := host_pcr_rep_valid
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io.host.pcr_rep.bits := host_pcr_bits.data
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when (io.host.pcr_req.fire()) {
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host_pcr_req_valid := true
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host_pcr_bits := io.host.pcr_req.bits
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}
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when (host_pcr_req_fire) {
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host_pcr_req_valid := false
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host_pcr_rep_valid := true
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host_pcr_bits.data := io.rw.rdata
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}
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when (io.host.pcr_rep.fire()) { host_pcr_rep_valid := false }
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io.host.debug_stats_pcr := reg_stats // direct export up the hierarchy
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val addr = Mux(cpu_req_valid, io.rw.addr, host_pcr_bits.addr | 0x500)
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val decoded_addr = {
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val default = List(Bits("b" + ("?"*CSRs.all.size), CSRs.all.size))
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val outs = for (i <- 0 until CSRs.all.size)
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yield UInt(CSRs.all(i), addr.getWidth) -> List(UInt(BigInt(1) << i, CSRs.all.size))
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val d = DecodeLogic(addr, default, outs).toArray
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val a = Array.fill(CSRs.all.max+1)(null.asInstanceOf[Bool])
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for (i <- 0 until CSRs.all.size)
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a(CSRs.all(i)) = d(0)(i)
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a
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}
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val wen = cpu_req_valid || host_pcr_req_fire && host_pcr_bits.rw
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val wdata = Mux(cpu_req_valid, io.rw.wdata, host_pcr_bits.data)
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io.status := reg_status
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io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false),
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Bool(false), irq_rocc, Bool(false), Bool(false))
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io.fatc := wen && decoded_addr(CSRs.fatc)
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io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt
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io.ptbr := reg_ptbr
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when (io.badvaddr_wen) {
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val wdata = io.rw.wdata
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val (upper, lower) = Split(wdata, VADDR_BITS)
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val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR)
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reg_badvaddr := Cat(sign, lower).toSInt
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}
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when (io.exception) {
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reg_status.s := true
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reg_status.ps := reg_status.s
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reg_status.ei := false
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reg_status.pei := reg_status.ei
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reg_epc := io.pc.toSInt
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reg_cause := io.cause
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}
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when (io.sret) {
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reg_status.s := reg_status.ps
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reg_status.ei := reg_status.pei
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}
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when (reg_time(reg_compare.getWidth-1,0) === reg_compare) {
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r_irq_timer := true
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}
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io.time := reg_time
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io.host.ipi_req.valid := cpu_req_valid && decoded_addr(CSRs.send_ipi)
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io.host.ipi_req.bits := io.rw.wdata
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io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
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when (host_pcr_req_fire && !host_pcr_bits.rw && decoded_addr(CSRs.tohost)) { reg_tohost := UInt(0) }
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val read_impl = Bits(2)
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val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS
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val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
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CSRs.fflags -> (if (!conf.fpu.isEmpty) reg_fflags else UInt(0)),
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CSRs.frm -> (if (!conf.fpu.isEmpty) reg_frm else UInt(0)),
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CSRs.fcsr -> (if (!conf.fpu.isEmpty) Cat(reg_frm, reg_fflags) else UInt(0)),
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CSRs.cycle -> reg_time,
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CSRs.time -> reg_time,
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CSRs.instret -> reg_instret,
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CSRs.sup0 -> reg_sup0,
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CSRs.sup1 -> reg_sup1,
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CSRs.epc -> reg_epc,
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CSRs.badvaddr -> reg_badvaddr,
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CSRs.ptbr -> read_ptbr,
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CSRs.asid -> UInt(0),
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CSRs.count -> reg_time,
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CSRs.compare -> reg_compare,
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CSRs.evec -> reg_evec,
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CSRs.cause -> reg_cause,
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CSRs.status -> io.status.toBits,
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CSRs.hartid -> io.host.id,
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CSRs.impl -> read_impl,
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CSRs.fatc -> read_impl, // don't care
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CSRs.send_ipi -> read_impl, // don't care
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CSRs.clear_ipi -> read_impl, // don't care
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CSRs.stats -> reg_stats,
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CSRs.tohost -> reg_tohost,
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CSRs.fromhost -> reg_fromhost)
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for (i <- 0 until reg_uarch_counters.size)
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read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i)
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io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
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io.fcsr_rm := reg_frm
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when (io.fcsr_flags.valid) {
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reg_fflags := reg_fflags | io.fcsr_flags.bits
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}
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when (wen) {
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when (decoded_addr(CSRs.status)) {
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reg_status := new Status().fromBits(wdata)
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reg_status.s64 := true
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reg_status.u64 := true
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reg_status.zero := 0
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if (!conf.vm) reg_status.vm := false
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if (conf.rocc.isEmpty) reg_status.er := false
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if (conf.fpu.isEmpty) reg_status.ef := false
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}
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when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
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when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
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when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
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when (decoded_addr(CSRs.epc)) { reg_epc := wdata(VADDR_BITS,0).toSInt }
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when (decoded_addr(CSRs.evec)) { reg_evec := wdata(VADDR_BITS-1,0).toSInt }
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when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt }
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when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false) }
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when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
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when (decoded_addr(CSRs.tohost)) { when (reg_tohost === UInt(0) || host_pcr_req_fire) { reg_tohost := wdata } }
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when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) }
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when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata }
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when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata }
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when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt }
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when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) }
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}
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io.host.ipi_rep.ready := Bool(true)
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when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) }
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when(this.reset) {
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reg_status.ei := false
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reg_status.pei := false
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reg_status.ef := false
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reg_status.er := false
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reg_status.ps := false
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reg_status.s := true
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reg_status.u64 := true
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reg_status.s64 := true
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reg_status.vm := false
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reg_status.zero := 0
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reg_status.im := 0
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reg_status.ip := 0
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}
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}
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