riscv/rocket-chip
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fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/

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Colin Schmidt 2015-03-10 10:28:05 -07:00
parent 95aa295c39
commit e293d89035
1 changed files with 4 additions and 4 deletions
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8
rocket/src/main/scala/decode.scala
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@ -159,10 +159,10 @@ object SimplifyDC
def getImplicitDC(maxterms: Seq[Term], term: Term, bits: Int, above: Boolean): Term = { def getImplicitDC(maxterms: Seq[Term], term: Term, bits: Int, above: Boolean): Term = {
for (i <- 0 until bits) { for (i <- 0 until bits) {
var t: Term = null var t: Term = null
if (above && ((term.value | term.mask) & (1L << i)) == 0) if (above && ((term.value | term.mask) & (BigInt(1) << i)) == 0)
t = new Term(term.value | (1L << i), term.mask) t = new Term(term.value | (BigInt(1) << i), term.mask)
else if (!above && (term.value & (1L << i)) != 0) else if (!above && (term.value & (BigInt(1) << i)) != 0)
t = new Term(term.value & ~(1L << i), term.mask) t = new Term(term.value & ~(BigInt(1) << i), term.mask)
if (t != null && !maxterms.exists(_.intersects(t))) if (t != null && !maxterms.exists(_.intersects(t)))
return t return t
} }