riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

refactor code related to vector exceptions

Browse Source 
- revisied interfaces
- new instructions
This commit is contained in:
Yunsup Lee
2012-03-03 15:09:42 -08:00
parent f9fb3978ca
commit e28a551368
7 changed files with 158 additions and 96 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
rocket/src/main/scala/consts.scala
View File

@ -244,12 +244,17 @@ object Constants
val VCMD_TF = UFix(3, 3)
val VCMD_MX = UFix(4, 3)
val VCMD_MF = UFix(5, 3)
val VCMD_A = UFix(6, 3)
val VCMD_X = UFix(0, 3)
val VIMM_VLEN = UFix(0, 1)
val VIMM_ALU = UFix(1, 1)
val VIMM_X = UFix(0, 1)
val VIMM2_RS2 = UFix(0, 1)
val VIMM2_ALU = UFix(1, 1)
val VIMM2_X = UFix(0, 1)
val DTLB_CPU = 0
val DTLB_VEC = 1
val DTLB_VPF = 2