riscv/rocket-chip
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Improve ChiselConfig composability; bump chisel

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This commit is contained in:
Yunsup Lee 2014-10-06 13:43:40 -07:00
parent 73eac94a65
commit e25d420155
2 changed files with 131 additions and 154 deletions
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2
chisel

@ -1 +1 @@
Subproject commit cae89773b50175a16b170f1c38271247b628914b Subproject commit c9ed7da52aa7e58672dc231469e5033a29f4c2ef

283
src/main/scala/PublicConfigs.scala
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@ -7,125 +7,121 @@ import uncore._
import rocket._ import rocket._
import rocket.Util._ import rocket.Util._
class DefaultConfig extends ChiselConfig { class DefaultConfig extends ChiselConfig (
type PF = PartialFunction[Any,Any] topDefinitions = { (pname,site,here) =>
val topDefinitions:World.TopDefs = { type PF = PartialFunction[Any,Any]
(pname,site,here) => { def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname) pname match {
pname match { //RocketChip Parameters
//RocketChip Parameters case BuildTile => (r:Bool) => {new RocketTile(resetSignal = r)}
case BuildTile => (r:Bool) => {new RocketTile(resetSignal = r)} //HTIF Parameters
//HTIF Parameters case HTIFWidth => Dump("HTIF_WIDTH", 16)
case HTIFWidth => Dump("HTIF_WIDTH", 16) case HTIFNSCR => 64
case HTIFNSCR => 64 case HTIFOffsetBits => site(CacheBlockOffsetBits)
case HTIFOffsetBits => site(CacheBlockOffsetBits) case HTIFNCores => site(NTiles)
case HTIFNCores => site(NTiles) //Memory Parameters
//Memory Parameters case PAddrBits => 32
case PAddrBits => 32 case VAddrBits => 43
case VAddrBits => 43 case PgIdxBits => 13
case PgIdxBits => 13 case ASIdBits => 7
case ASIdBits => 7 case PermBits => 6
case PermBits => 6 case PPNBits => site(PAddrBits) - site(PgIdxBits)
case PPNBits => site(PAddrBits) - site(PgIdxBits) case VPNBits => site(VAddrBits) - site(PgIdxBits)
case VPNBits => site(VAddrBits) - site(PgIdxBits) case MIFTagBits => Dump("MEM_TAG_BITS", 5)
case MIFTagBits => Dump("MEM_TAG_BITS", 5) case MIFDataBits => Dump("MEM_DATA_BITS", 128)
case MIFDataBits => Dump("MEM_DATA_BITS", 128) case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits)) case MIFDataBeats => site(TLDataBits)/site(MIFDataBits)
case MIFDataBeats => site(TLDataBits)/site(MIFDataBits) //Params used by all caches
//Params used by all caches case NSets => findBy(CacheName)
case NSets => findBy(CacheName) case NWays => findBy(CacheName)
case NWays => findBy(CacheName) case RowBits => findBy(CacheName)
case RowBits => findBy(CacheName) case BlockOffBits => findBy(CacheName)
case BlockOffBits => findBy(CacheName) case "L1I" => {
case ECCCode => None case NSets => Knob("L1I_SETS") //128
case WordBits => site(XprLen) case NWays => Knob("L1I_WAYS") //2
case Replacer => () => new RandomReplacement(site(NWays)) case RowBits => 4*site(CoreInstBits)
//Cache-Specific Params case BlockOffBits => log2Up(site(TLDataBits)/8)
case "L1I" => { }:PF
case NSets => 128 case "L1D" => {
case NWays => 2 case NSets => Knob("L1D_SETS") //128
case RowBits => 4*site(CoreInstBits) case NWays => Knob("L1D_WAYS") //4
case BlockOffBits => log2Up(site(TLDataBits)/8) case RowBits => 2*site(CoreDataBits)
}:PF case BlockOffBits => log2Up(site(TLDataBits)/8)
case "L1D" => { }:PF
case NSets => Knob("L1D_SETS") //128 case "L2" => {
case NWays => Knob("L1D_WAYS") //4 case NSets => 512
case RowBits => 2*site(CoreDataBits) case NWays => 8
case BlockOffBits => log2Up(site(TLDataBits)/8) case RowBits => site(TLDataBits)
}:PF case BlockOffBits => 0
case "L2" => { }:PF
case NSets => 512 case ECCCode => None
case NWays => 8 case WordBits => site(XprLen)
case RowBits => site(TLDataBits) case Replacer => () => new RandomReplacement(site(NWays))
case BlockOffBits => 0 //L1InstCache
}:PF case NITLBEntries => 8
//L1InstCache case NBTBEntries => 62
case NITLBEntries => 8 case NRAS => 2
case NBTBEntries => 62 //L1DataCache
case NRAS => 2 case NDTLBEntries => 8
//L1DataCache case StoreDataQueueDepth => 17
case NDTLBEntries => 8 case ReplayQueueDepth => 16
case StoreDataQueueDepth => 17 case NMSHRs => Knob("L1D_MSHRS")
case ReplayQueueDepth => 16 case LRSCCycles => 32
case NMSHRs => Knob("L1D_MSHRS") //L2CacheParams
case LRSCCycles => 32 case NReleaseTransactors => Knob("L2_REL_XACTS")
//L2CacheParams case NAcquireTransactors => Knob("L2_ACQ_XACTS")
case NReleaseTransactors => Knob("L2_REL_XACTS") case NClients => site(NTiles) + 1
case NAcquireTransactors => Knob("L2_ACQ_XACTS") //Tile Constants
case NClients => site(NTiles) + 1 case BuildRoCC => None
//Tile Constants case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
case BuildRoCC => None case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1) case NPTWPorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 3)
case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1) //Rocket Core Constants
case NPTWPorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 3) case RetireWidth => 1
//Rocket Core Constants case UseVM => true
case RetireWidth => 1 case FastLoadWord => true
case UseVM => true case FastLoadByte => false
case FastLoadWord => true case FastMulDiv => true
case FastLoadByte => false case XprLen => 64
case FastMulDiv => true case NMultXpr => 32
case XprLen => 64 case BuildFPU => Some(() => Module(new FPU))
case NMultXpr => 32 case SFMALatency => 2
case BuildFPU => Some(() => Module(new FPU)) case DFMALatency => 3
case SFMALatency => 2 case CoreInstBits => 32
case DFMALatency => 3 case CoreDataBits => site(XprLen)
case CoreInstBits => 32 case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
case CoreDataBits => site(XprLen) //Uncore Paramters
case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts)) case LNMasters => site(NBanks)
//Uncore Paramters case LNClients => site(NTiles)+1
case LNMasters => site(NBanks) case LNEndpoints => site(LNMasters) + site(LNClients)
case LNClients => site(NTiles)+1 case TLId => "inner"
case LNEndpoints => site(LNMasters) + site(LNClients) case TLCoherence => site(Coherence)
case TLId => "inner" case TLAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
case TLCoherence => site(Coherence) case TLMasterXactIdBits => site(TLId) match {
case TLAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits) case "inner" => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
case TLMasterXactIdBits => site(TLId) match { case "outer" => 1
case "inner" => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
case "outer" => 1
}
case TLClientXactIdBits => site(TLId) match {
case "inner" => log2Up(site(NMSHRs))+log2Up(site(NTilePorts))
case "outer" => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
}
case TLDataBits => site(CacheBlockBytes)*8
case TLWriteMaskBits => 6
case TLWordAddrBits => 3
case TLAtomicOpBits => 4
case NTiles => Knob("NTILES")
case NBanks => Knob("NBANKS")
case NOutstandingMemReqs => 16 //site(NBanks)*(site(NReleaseTransactors)+site(NAcquireTransactors))
case BankIdLSB => 5
case CacheBlockBytes => 64
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
case UseBackupMemoryPort => true
case BuildCoherenceMaster => (id: Int) => {
Module(new L2CoherenceAgent(id, "inner", "outer"), { case CacheName => "L2" })
}
case Coherence => new MSICoherence(() => new NullRepresentation)
} }
} case TLClientXactIdBits => site(TLId) match {
} case "inner" => log2Up(site(NMSHRs))+log2Up(site(NTilePorts))
override val knobValues:Any=>Any = { case "outer" => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
}
case TLDataBits => site(CacheBlockBytes)*8
case TLWriteMaskBits => 6
case TLWordAddrBits => 3
case TLAtomicOpBits => 4
case NTiles => Knob("NTILES")
case NBanks => Knob("NBANKS")
case NOutstandingMemReqs => 2*site(NBanks)*(site(NReleaseTransactors)+site(NAcquireTransactors))
case BankIdLSB => 5
case CacheBlockBytes => 64
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
case UseBackupMemoryPort => true
case BuildCoherenceMaster => (id: Int) => {
Module(new L2CoherenceAgent(id, "inner", "outer"), { case CacheName => "L2" })
}
case Coherence => new MSICoherence(() => new NullRepresentation)
}},
knobValues = {
case "NTILES" => 1 case "NTILES" => 1
case "NBANKS" => 1 case "NBANKS" => 1
case "L2_REL_XACTS" => 1 case "L2_REL_XACTS" => 1
@ -133,54 +129,35 @@ class DefaultConfig extends ChiselConfig {
case "L1D_MSHRS" => 2 case "L1D_MSHRS" => 2
case "L1D_SETS" => 128 case "L1D_SETS" => 128
case "L1D_WAYS" => 4 case "L1D_WAYS" => 4
case "L1I_SETS" => 128
case "L1I_WAYS" => 2
} }
} )
class DefaultVLSIConfig extends DefaultConfig class DefaultVLSIConfig extends DefaultConfig
class DefaultCPPConfig extends DefaultConfig class DefaultCPPConfig extends DefaultConfig
class FPGAConfig extends ChiselConfig (
class FPGAConfig(default: ChiselConfig) extends ChiselConfig { (pname,site,here) => pname match {
val topDefinitions:World.TopDefs = { case UseBackupMemoryPort => false
(pname,site,here) => pname match {
case UseBackupMemoryPort => false
case _ => default.topDefinitions(pname,site,here)
}
} }
override val knobValues = default.knobValues )
}
class DefaultFPGAConfig extends FPGAConfig(new DefaultConfig) class DefaultFPGAConfig extends ChiselConfig(new FPGAConfig ++ new DefaultConfig)
class FPGASmallConfig extends ChiselConfig (
class FPGASmallConfig(default: ChiselConfig) extends ChiselConfig { topDefinitions = { (pname,site,here) => pname match {
val topDefinitions:World.TopDefs = {
(pname,site,here) => pname match {
case NSets => site(CacheName) match {
case "L1I" => 64
case "L1D" => Knob("L1D_SETS")
}
case NWays => site(CacheName) match {
case "L1I" => 1
case "L1D" => Knob("L1D_WAYS")
}
case BuildFPU => None case BuildFPU => None
case FastMulDiv => false case FastMulDiv => false
case NITLBEntries => 4 case NITLBEntries => 4
case NBTBEntries => 8 case NBTBEntries => 8
case NDTLBEntries => 4 case NDTLBEntries => 4
case UseBackupMemoryPort => false }},
case _ => default.topDefinitions(pname,site,here) knobValues = {
}
}
override val knobValues:Any=>Any = {
case "NTILES" => 1
case "NBANKS" => 1
case "L2_REL_XACTS" => 1
case "L2_ACQ_XACTS" => 7
case "L1D_MSHRS" => 2
case "L1D_SETS" => 64 case "L1D_SETS" => 64
case "L1D_WAYS" => 1 case "L1D_WAYS" => 1
case "L1I_SETS" => 64
case "L1I_WAYS" => 1
} }
} )
class DefaultFPGASmallConfig extends FPGASmallConfig(new FPGAConfig(new DefaultConfig)) class DefaultFPGASmallConfig extends ChiselConfig(new FPGASmallConfig ++ new DefaultFPGAConfig)