riscv/rocket-chip
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Improve ChiselConfig composability; bump chisel

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This commit is contained in:
Yunsup Lee 2014-10-06 13:43:40 -07:00
parent 73eac94a65
commit e25d420155
2 changed files with 131 additions and 154 deletions
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2
chisel

@ -1 +1 @@
Subproject commit cae89773b50175a16b170f1c38271247b628914b Subproject commit c9ed7da52aa7e58672dc231469e5033a29f4c2ef

71
src/main/scala/PublicConfigs.scala
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@ -7,10 +7,9 @@ import uncore._
import rocket._ import rocket._
import rocket.Util._ import rocket.Util._
class DefaultConfig extends ChiselConfig { class DefaultConfig extends ChiselConfig (
topDefinitions = { (pname,site,here) =>
type PF = PartialFunction[Any,Any] type PF = PartialFunction[Any,Any]
val topDefinitions:World.TopDefs = {
(pname,site,here) => {
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname) def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
pname match { pname match {
//RocketChip Parameters //RocketChip Parameters
@ -37,13 +36,9 @@ class DefaultConfig extends ChiselConfig {
case NWays => findBy(CacheName) case NWays => findBy(CacheName)
case RowBits => findBy(CacheName) case RowBits => findBy(CacheName)
case BlockOffBits => findBy(CacheName) case BlockOffBits => findBy(CacheName)
case ECCCode => None
case WordBits => site(XprLen)
case Replacer => () => new RandomReplacement(site(NWays))
//Cache-Specific Params
case "L1I" => { case "L1I" => {
case NSets => 128 case NSets => Knob("L1I_SETS") //128
case NWays => 2 case NWays => Knob("L1I_WAYS") //2
case RowBits => 4*site(CoreInstBits) case RowBits => 4*site(CoreInstBits)
case BlockOffBits => log2Up(site(TLDataBits)/8) case BlockOffBits => log2Up(site(TLDataBits)/8)
}:PF }:PF
@ -59,6 +54,9 @@ class DefaultConfig extends ChiselConfig {
case RowBits => site(TLDataBits) case RowBits => site(TLDataBits)
case BlockOffBits => 0 case BlockOffBits => 0
}:PF }:PF
case ECCCode => None
case WordBits => site(XprLen)
case Replacer => () => new RandomReplacement(site(NWays))
//L1InstCache //L1InstCache
case NITLBEntries => 8 case NITLBEntries => 8
case NBTBEntries => 62 case NBTBEntries => 62
@ -113,7 +111,7 @@ class DefaultConfig extends ChiselConfig {
case TLAtomicOpBits => 4 case TLAtomicOpBits => 4
case NTiles => Knob("NTILES") case NTiles => Knob("NTILES")
case NBanks => Knob("NBANKS") case NBanks => Knob("NBANKS")
case NOutstandingMemReqs => 16 //site(NBanks)*(site(NReleaseTransactors)+site(NAcquireTransactors)) case NOutstandingMemReqs => 2*site(NBanks)*(site(NReleaseTransactors)+site(NAcquireTransactors))
case BankIdLSB => 5 case BankIdLSB => 5
case CacheBlockBytes => 64 case CacheBlockBytes => 64
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes)) case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
@ -122,10 +120,8 @@ class DefaultConfig extends ChiselConfig {
Module(new L2CoherenceAgent(id, "inner", "outer"), { case CacheName => "L2" }) Module(new L2CoherenceAgent(id, "inner", "outer"), { case CacheName => "L2" })
} }
case Coherence => new MSICoherence(() => new NullRepresentation) case Coherence => new MSICoherence(() => new NullRepresentation)
} }},
} knobValues = {
}
override val knobValues:Any=>Any = {
case "NTILES" => 1 case "NTILES" => 1
case "NBANKS" => 1 case "NBANKS" => 1
case "L2_REL_XACTS" => 1 case "L2_REL_XACTS" => 1
@ -133,54 +129,35 @@ class DefaultConfig extends ChiselConfig {
case "L1D_MSHRS" => 2 case "L1D_MSHRS" => 2
case "L1D_SETS" => 128 case "L1D_SETS" => 128
case "L1D_WAYS" => 4 case "L1D_WAYS" => 4
case "L1I_SETS" => 128
case "L1I_WAYS" => 2
} }
} )
class DefaultVLSIConfig extends DefaultConfig class DefaultVLSIConfig extends DefaultConfig
class DefaultCPPConfig extends DefaultConfig class DefaultCPPConfig extends DefaultConfig
class FPGAConfig extends ChiselConfig (
class FPGAConfig(default: ChiselConfig) extends ChiselConfig {
val topDefinitions:World.TopDefs = {
(pname,site,here) => pname match { (pname,site,here) => pname match {
case UseBackupMemoryPort => false case UseBackupMemoryPort => false
case _ => default.topDefinitions(pname,site,here)
}
}
override val knobValues = default.knobValues
} }
)
class DefaultFPGAConfig extends FPGAConfig(new DefaultConfig) class DefaultFPGAConfig extends ChiselConfig(new FPGAConfig ++ new DefaultConfig)
class FPGASmallConfig extends ChiselConfig (
class FPGASmallConfig(default: ChiselConfig) extends ChiselConfig { topDefinitions = { (pname,site,here) => pname match {
val topDefinitions:World.TopDefs = {
(pname,site,here) => pname match {
case NSets => site(CacheName) match {
case "L1I" => 64
case "L1D" => Knob("L1D_SETS")
}
case NWays => site(CacheName) match {
case "L1I" => 1
case "L1D" => Knob("L1D_WAYS")
}
case BuildFPU => None case BuildFPU => None
case FastMulDiv => false case FastMulDiv => false
case NITLBEntries => 4 case NITLBEntries => 4
case NBTBEntries => 8 case NBTBEntries => 8
case NDTLBEntries => 4 case NDTLBEntries => 4
case UseBackupMemoryPort => false }},
case _ => default.topDefinitions(pname,site,here) knobValues = {
}
}
override val knobValues:Any=>Any = {
case "NTILES" => 1
case "NBANKS" => 1
case "L2_REL_XACTS" => 1
case "L2_ACQ_XACTS" => 7
case "L1D_MSHRS" => 2
case "L1D_SETS" => 64 case "L1D_SETS" => 64
case "L1D_WAYS" => 1 case "L1D_WAYS" => 1
case "L1I_SETS" => 64
case "L1I_WAYS" => 1
} }
} )
class DefaultFPGASmallConfig extends FPGASmallConfig(new FPGAConfig(new DefaultConfig)) class DefaultFPGASmallConfig extends ChiselConfig(new FPGASmallConfig ++ new DefaultFPGAConfig)