riscv/rocket-chip
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Size hartid field with NTiles, not XLen

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This commit is contained in:
Andrew Waterman
2017-04-26 20:11:43 -07:00
parent dc753bfa95
commit e23ee274f6
7 changed files with 16 additions and 15 deletions
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4
src/main/scala/tile/Core.scala
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@ -75,11 +75,11 @@ abstract class CoreModule(implicit val p: Parameters) extends Module
abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasCoreParameters
trait HasCoreIO {
trait HasCoreIO extends HasTileParameters {
implicit val p: Parameters
val io = new Bundle {
val interrupts = new TileInterrupts().asInput
val hartid = UInt(INPUT, p(XLen))
val hartid = UInt(INPUT, hartIdLen)
val imem = new FrontendIO()(p)
val dmem = new HellaCacheIO()(p)
val ptw = new DatapathPTWIO().flip