riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Size hartid field with NTiles, not XLen

Browse Source
This commit is contained in:
Andrew Waterman
2017-04-26 20:11:43 -07:00
parent dc753bfa95
commit e23ee274f6
7 changed files with 16 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/tile/BaseTile.scala
View File

@ -31,6 +31,7 @@ trait HasTileParameters {
val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
val usingPTW = usingVM
val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined
val hartIdLen = log2Up(p(uncore.devices.NTiles))
def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
}
@ -71,9 +72,10 @@ abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends
}
class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
with HasTileParameters
with HasTileLinkMasterPortBundle
with HasExternalInterruptsBundle {
val hartid = UInt(INPUT, p(XLen))
val hartid = UInt(INPUT, hartIdLen)
val resetVector = UInt(INPUT, p(XLen))
}