Size hartid field with NTiles, not XLen

src/main/scala/tile/BaseTile.scala

@@ -31,6 +31,7 @@ trait HasTileParameters {
   val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
   val usingPTW = usingVM
   val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined
+  val hartIdLen = log2Up(p(uncore.devices.NTiles))
 
   def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
 }
@@ -71,9 +72,10 @@ abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends
 }
 
 class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
+    with HasTileParameters
     with HasTileLinkMasterPortBundle
     with HasExternalInterruptsBundle {
-  val hartid = UInt(INPUT, p(XLen))
+  val hartid = UInt(INPUT, hartIdLen)
   val resetVector = UInt(INPUT, p(XLen))
 }
 

src/main/scala/tile/Core.scala

@@ -75,11 +75,11 @@ abstract class CoreModule(implicit val p: Parameters) extends Module
 abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
   with HasCoreParameters
 
-trait HasCoreIO {
+trait HasCoreIO extends HasTileParameters {
   implicit val p: Parameters
   val io = new Bundle {
     val interrupts = new TileInterrupts().asInput
-    val hartid = UInt(INPUT, p(XLen))
+    val hartid = UInt(INPUT, hartIdLen)
     val imem  = new FrontendIO()(p)
     val dmem = new HellaCacheIO()(p)
     val ptw = new DatapathPTWIO().flip