riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Size hartid field with NTiles, not XLen

Browse Source
This commit is contained in:
Andrew Waterman
2017-04-26 20:11:43 -07:00
parent dc753bfa95
commit e23ee274f6
7 changed files with 16 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/ICache.scala
View File

@ -55,7 +55,7 @@ class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends
}
class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
val hartid = UInt(INPUT, p(XLen))
val hartid = UInt(INPUT, hartIdLen)
val req = Decoupled(new ICacheReq).flip
val s1_paddr = UInt(INPUT, paddrBits) // delayed one cycle w.r.t. req
val s2_vaddr = UInt(INPUT, vaddrBits) // delayed two cycles w.r.t. req