riscv/rocket-chip
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Size hartid field with NTiles, not XLen

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This commit is contained in:
Andrew Waterman
2017-04-26 20:11:43 -07:00
parent dc753bfa95
commit e23ee274f6
7 changed files with 16 additions and 15 deletions
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src/main/scala/rocket/Frontend.scala
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@ -61,7 +61,7 @@ class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p) {
val tl_out = outer.node.bundleOut
val tl_in = outer.slaveNode.map(_.bundleIn)
val resetVector = UInt(INPUT, vaddrBitsExtended)
val hartid = UInt(INPUT, p(XLen))
val hartid = UInt(INPUT, hartIdLen)
}
class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)