Size hartid field with NTiles, not XLen
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@ -153,7 +153,7 @@ class PerfCounterIO(implicit p: Parameters) extends CoreBundle
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class CSRFileIO(implicit p: Parameters) extends CoreBundle
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with HasRocketCoreParameters {
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val interrupts = new TileInterrupts().asInput
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val hartid = UInt(INPUT, xLen)
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val hartid = UInt(INPUT, hartIdLen)
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val rw = new Bundle {
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val addr = UInt(INPUT, CSR.ADDRSZ)
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val cmd = Bits(INPUT, CSR.SZ)
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