riscv/rocket-chip
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Size hartid field with NTiles, not XLen

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This commit is contained in:
Andrew Waterman
2017-04-26 20:11:43 -07:00
parent dc753bfa95
commit e23ee274f6
7 changed files with 16 additions and 15 deletions
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2
src/main/scala/rocket/CSR.scala
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@ -153,7 +153,7 @@ class PerfCounterIO(implicit p: Parameters) extends CoreBundle
class CSRFileIO(implicit p: Parameters) extends CoreBundle
with HasRocketCoreParameters {
val interrupts = new TileInterrupts().asInput
val hartid = UInt(INPUT, xLen)
val hartid = UInt(INPUT, hartIdLen)
val rw = new Bundle {
val addr = UInt(INPUT, CSR.ADDRSZ)
val cmd = Bits(INPUT, CSR.SZ)

2
src/main/scala/rocket/Frontend.scala
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@ -61,7 +61,7 @@ class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p) {
val tl_out = outer.node.bundleOut
val tl_in = outer.slaveNode.map(_.bundleIn)
val resetVector = UInt(INPUT, vaddrBitsExtended)
val hartid = UInt(INPUT, p(XLen))
val hartid = UInt(INPUT, hartIdLen)
}
class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)

5
src/main/scala/rocket/HellaCache.scala
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@ -158,9 +158,8 @@ abstract class HellaCache(implicit p: Parameters) extends LazyModule {
val module: HellaCacheModule
}
class HellaCacheBundle(outer: HellaCache) extends Bundle {
implicit val p = outer.p
val hartid = UInt(INPUT, p(XLen))
class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = UInt(INPUT, hartIdLen)
val cpu = (new HellaCacheIO).flip
val ptw = new TLBPTWIO()
val mem = outer.node.bundleOut

2
src/main/scala/rocket/ICache.scala
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@ -55,7 +55,7 @@ class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends
}
class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
val hartid = UInt(INPUT, p(XLen))
val hartid = UInt(INPUT, hartIdLen)
val req = Decoupled(new ICacheReq).flip
val s1_paddr = UInt(INPUT, paddrBits) // delayed one cycle w.r.t. req
val s2_vaddr = UInt(INPUT, vaddrBits) // delayed two cycles w.r.t. req

12
src/main/scala/rocket/Tile.scala
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@ -176,11 +176,11 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
xing.intnode := intNode
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val io = new CoreBundle {
val master = masterNode.bundleOut
val slave = slaveNode.bundleIn
val interrupts = intNode.bundleIn
val hartid = UInt(INPUT, p(XLen))
val hartid = UInt(INPUT, hartIdLen)
val resetVector = UInt(INPUT, p(XLen))
}
// signals that do not change:
@ -208,11 +208,11 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
xing.intnode := intNode
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val io = new CoreBundle {
val master = masterNode.bundleOut
val slave = slaveNode.bundleIn
val interrupts = intNode.bundleIn
val hartid = UInt(INPUT, p(XLen))
val hartid = UInt(INPUT, hartIdLen)
val resetVector = UInt(INPUT, p(XLen))
}
// signals that do not change:
@ -244,11 +244,11 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet
xing.intnode := intNode
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val io = new CoreBundle {
val master = masterNode.bundleOut
val slave = slaveNode.bundleIn
val interrupts = intNode.bundleIn
val hartid = UInt(INPUT, p(XLen))
val hartid = UInt(INPUT, hartIdLen)
val resetVector = UInt(INPUT, p(XLen))
}
// signals that do not change: