riscv/rocket-chip
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subsystem: XSubsystemModule => XSubsystemModuleImp

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This commit is contained in:
Henry Cook
2018-02-21 12:51:16 -08:00
parent 1af02f754e
commit e237f72539
4 changed files with 9 additions and 9 deletions
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4
src/main/scala/system/ExampleRocketSystem.scala
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@ -16,10 +16,10 @@ class ExampleRocketSystem(implicit p: Parameters) extends RocketSubsystem
with HasSlaveAXI4Port
with HasPeripheryBootROM
with HasSystemErrorSlave {
override lazy val module = new ExampleRocketSystemModule(this)
override lazy val module = new ExampleRocketSystemModuleImp(this)
}
class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends RocketSubsystemModule(_outer)
class ExampleRocketSystemModuleImp[+L <: ExampleRocketSystem](_outer: L) extends RocketSubsystemModuleImp(_outer)
with HasRTCModuleImp
with HasExtInterruptsModuleImp
with HasMasterAXI4MemPortModuleImp