riscv/rocket-chip
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subsystem: XSubsystemModule => XSubsystemModuleImp

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This commit is contained in:
Henry Cook
2018-02-21 12:51:16 -08:00
parent 1af02f754e
commit e237f72539
4 changed files with 9 additions and 9 deletions
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6
src/main/scala/subsystem/BaseSubsystem.scala
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@ -16,7 +16,7 @@ abstract class BareSubsystem(implicit p: Parameters) extends LazyModule with Bin
lazy val json = JSON(bindingTree)
}
abstract class BareSubsystemModule[+L <: BareSubsystem](_outer: L) extends LazyModuleImp(_outer) {
abstract class BareSubsystemModuleImp[+L <: BareSubsystem](_outer: L) extends LazyModuleImp(_outer) {
val outer = _outer
ElaborationArtefacts.add("graphml", outer.graphML)
ElaborationArtefacts.add("dts", outer.dts)
@ -27,7 +27,7 @@ abstract class BareSubsystemModule[+L <: BareSubsystem](_outer: L) extends LazyM
/** Base Subsystem class with no peripheral devices or ports added */
abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem {
override val module: BaseSubsystemModule[BaseSubsystem]
override val module: BaseSubsystemModuleImp[BaseSubsystem]
// These are wrappers around the standard buses available in all subsytems, where
// peripherals, tiles, ports, and other masters and slaves can attach themselves.
@ -97,7 +97,7 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem {
}
}
abstract class BaseSubsystemModule[+L <: BaseSubsystem](_outer: L) extends BareSubsystemModule(_outer) {
abstract class BaseSubsystemModuleImp[+L <: BaseSubsystem](_outer: L) extends BareSubsystemModuleImp(_outer) {
println("Generated Address Map")
private val aw = (outer.sbus.busView.bundle.addressBits-1)/4 + 1
private val fmt = s"\t%${aw}x - %${aw}x %c%c%c%c%c %s"