riscv/rocket-chip
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subsystem: XSubsystemModule => XSubsystemModuleImp

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This commit is contained in:
Henry Cook
2018-02-21 12:51:16 -08:00
parent 1af02f754e
commit e237f72539
4 changed files with 9 additions and 9 deletions
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src/main/scala/groundtest/GroundTestSubsystem.scala
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@ -33,10 +33,10 @@ class GroundTestSubsystem(implicit p: Parameters) extends BaseSubsystem
// No PLIC in ground test; so just sink the interrupts to nowhere
IntSinkNode(IntSinkPortSimple()) := ibus.toPLIC
override lazy val module = new GroundTestSubsystemModule(this)
override lazy val module = new GroundTestSubsystemModuleImp(this)
}
class GroundTestSubsystemModule[+L <: GroundTestSubsystem](_outer: L) extends BaseSubsystemModule(_outer)
class GroundTestSubsystemModuleImp[+L <: GroundTestSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasMasterAXI4MemPortModuleImp {
val success = IO(Bool(OUTPUT))