riscv/rocket-chip
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debug: Don't reset debugint register, as none of the interrupt registers are.

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This commit is contained in:
Megan Wachs 2017-06-27 14:10:13 -07:00
parent 136e4b6c27
commit e1fe0f245b
1 changed files with 2 additions and 1 deletions
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src/main/scala/rocket/CSR.scala
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@ -212,7 +212,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
reset_dcsr.xdebugver := 1 reset_dcsr.xdebugver := 1
reset_dcsr.prv := PRV.M reset_dcsr.prv := PRV.M
val reg_dcsr = Reg(init=reset_dcsr) val reg_dcsr = Reg(init=reset_dcsr)
val reg_debugint = Reg(init=Bool(false), next=io.interrupts.debug) val reg_debugint = Reg(Bool())
val (supported_interrupts, delegable_interrupts) = { val (supported_interrupts, delegable_interrupts) = {
val sup = Wire(new MIP) val sup = Wire(new MIP)
@ -720,6 +720,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
reg_mip.mtip := io.interrupts.mtip reg_mip.mtip := io.interrupts.mtip
reg_mip.msip := io.interrupts.msip reg_mip.msip := io.interrupts.msip
reg_mip.meip := io.interrupts.meip reg_mip.meip := io.interrupts.meip
reg_debugint := io.interrupts.debug
if (!usingVM) { if (!usingVM) {
reg_mideleg := 0 reg_mideleg := 0