From e1fe0f245bdd13a5b90a3e77c681446dbd780298 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 27 Jun 2017 14:10:13 -0700 Subject: [PATCH] debug: Don't reset debugint register, as none of the interrupt registers are. --- src/main/scala/rocket/CSR.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 323477e4..ab2f3d73 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -212,7 +212,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param reset_dcsr.xdebugver := 1 reset_dcsr.prv := PRV.M val reg_dcsr = Reg(init=reset_dcsr) - val reg_debugint = Reg(init=Bool(false), next=io.interrupts.debug) + val reg_debugint = Reg(Bool()) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) @@ -720,6 +720,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param reg_mip.mtip := io.interrupts.mtip reg_mip.msip := io.interrupts.msip reg_mip.meip := io.interrupts.meip + reg_debugint := io.interrupts.debug if (!usingVM) { reg_mideleg := 0