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simplify TileLinkParameters with Option

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This commit is contained in:
Henry Cook 2015-10-16 18:24:02 -07:00
parent 49667aa4b0
commit e1f573918d
2 changed files with 7 additions and 5 deletions
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4
uncore/src/main/scala/broadcast.scala
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@ -32,8 +32,8 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
val inStoreQueue :: inVolWBQueue :: inClientReleaseQueue :: Nil = Enum(UInt(), nDataQueueLocations) val inStoreQueue :: inVolWBQueue :: inClientReleaseQueue :: Nil = Enum(UInt(), nDataQueueLocations)
val usingStoreDataQueue = p.alterPartial({ val usingStoreDataQueue = p.alterPartial({
case TLKey(`innerTLId`) => innerTLParams.copy()(internalDataBits, innerWriteMaskBits) case TLKey(`innerTLId`) => innerTLParams.copy(overrideDataBitsPerBeat = Some(internalDataBits))
case TLKey(`outerTLId`) => outerTLParams.copy()(internalDataBits, outerWriteMaskBits) case TLKey(`outerTLId`) => outerTLParams.copy(overrideDataBitsPerBeat = Some(internalDataBits))
}) })
// Create SHRs for outstanding transactions // Create SHRs for outstanding transactions

8
uncore/src/main/scala/tilelink.scala
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@ -33,10 +33,12 @@ case class TileLinkParameters(
maxManagerXacts: Int, maxManagerXacts: Int,
addrBits: Int, addrBits: Int,
dataBits: Int, dataBits: Int,
dataBeats: Int = 4) dataBeats: Int = 4,
(val dataBitsPerBeat: Int = dataBits / dataBeats, overrideDataBitsPerBeat: Option[Int] = None
val writeMaskBits: Int = ((dataBits / dataBeats) - 1) / 8 + 1) { ) {
val nClients = nCachingClients + nCachelessClients val nClients = nCachingClients + nCachelessClients
val writeMaskBits: Int = ((dataBits / dataBeats) - 1) / 8 + 1
val dataBitsPerBeat: Int = overrideDataBitsPerBeat.getOrElse(dataBits / dataBeats)
} }