diff --git a/uncore/src/main/scala/broadcast.scala b/uncore/src/main/scala/broadcast.scala
index b7b4f9a7..7570d37b 100644
--- a/uncore/src/main/scala/broadcast.scala
+++ b/uncore/src/main/scala/broadcast.scala
@@ -32,8 +32,8 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
   val inStoreQueue :: inVolWBQueue :: inClientReleaseQueue :: Nil = Enum(UInt(), nDataQueueLocations)
 
   val usingStoreDataQueue = p.alterPartial({
-    case TLKey(`innerTLId`) => innerTLParams.copy()(internalDataBits, innerWriteMaskBits)
-    case TLKey(`outerTLId`) => outerTLParams.copy()(internalDataBits, outerWriteMaskBits)
+    case TLKey(`innerTLId`) => innerTLParams.copy(overrideDataBitsPerBeat = Some(internalDataBits))
+    case TLKey(`outerTLId`) => outerTLParams.copy(overrideDataBitsPerBeat = Some(internalDataBits))
   })
 
   // Create SHRs for outstanding transactions
diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala
index feb930c2..7d7c7ffd 100644
--- a/uncore/src/main/scala/tilelink.scala
+++ b/uncore/src/main/scala/tilelink.scala
@@ -33,10 +33,12 @@ case class TileLinkParameters(
     maxManagerXacts: Int,
     addrBits: Int,
     dataBits: Int,
-    dataBeats: Int = 4)
-    (val dataBitsPerBeat: Int = dataBits / dataBeats,
-     val writeMaskBits: Int  = ((dataBits / dataBeats) - 1) / 8 + 1) {
+    dataBeats: Int = 4,
+    overrideDataBitsPerBeat: Option[Int] = None
+    ) {
   val nClients = nCachingClients + nCachelessClients
+  val writeMaskBits: Int  = ((dataBits / dataBeats) - 1) / 8 + 1
+  val dataBitsPerBeat: Int = overrideDataBitsPerBeat.getOrElse(dataBits / dataBeats)
 }