riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

simplify TileLinkParameters with Option

Browse Source
This commit is contained in:
Henry Cook committed 2015-10-16 18:24:38 -07:00
1 parent 49667aa4b0
commit e1f573918d
2 files changed
+7 -5
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

uncore/src/main/scala/broadcast.scala
+2 -2
View File
@@ -32,8 +32,8 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
val inStoreQueue :: inVolWBQueue :: inClientReleaseQueue :: Nil = Enum(UInt(), nDataQueueLocations)
val usingStoreDataQueue = p.alterPartial({
case TLKey(`innerTLId`) => innerTLParams.copy()(internalDataBits, innerWriteMaskBits)
case TLKey(`outerTLId`) => outerTLParams.copy()(internalDataBits, outerWriteMaskBits)
case TLKey(`innerTLId`) => innerTLParams.copy(overrideDataBitsPerBeat = Some(internalDataBits))
case TLKey(`outerTLId`) => outerTLParams.copy(overrideDataBitsPerBeat = Some(internalDataBits))
})
// Create SHRs for outstanding transactions