riscv/rocket-chip
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fix issue with partial writemasks

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Howard Mao
2016-03-24 19:52:12 -07:00
parent 6c48dc3471
commit e1a03cc9ac
3 changed files with 6 additions and 2 deletions
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2
groundtest

Submodule groundtest updated: e711f7988f...109f29e0ae

4
src/main/scala/TestConfigs.scala
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@@ -35,6 +35,8 @@ class WithGroundTest extends Config(
} }
} }
case GroundTestMaxXacts => 1 case GroundTestMaxXacts => 1
case GroundTestCSRs => Nil
case RoccNCSRs => site(GroundTestCSRs).size
case UseFPU => false case UseFPU => false
}) })
@@ -101,6 +103,8 @@ class WithDmaStreamTest extends Config(
case DmaStreamTestSettings => DmaStreamTestConfig( case DmaStreamTestSettings => DmaStreamTestConfig(
source = 0x10, dest = 0x28, len = 0x18, source = 0x10, dest = 0x28, len = 0x18,
size = site(StreamLoopbackWidth) / 8) size = site(StreamLoopbackWidth) / 8)
case GroundTestCSRs =>
Seq(DmaCtrlRegNumbers.CSR_BASE + DmaCtrlRegNumbers.OUTSTANDING)
}) })
class WithNastiConverterTest extends Config( class WithNastiConverterTest extends Config(

2
uncore

Submodule uncore updated: 86f6845288...9978139f4f