riscv/rocket-chip
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Use 1-entry queue on processor-side E-channel

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The cache can't sink a grant every cycle, so extra E buffering doesn't help.
This commit is contained in:
Andrew Waterman 2017-07-31 18:06:54 -07:00
parent 5681693ccc
commit e140893a01
1 changed files with 1 additions and 1 deletions
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src/main/scala/tile/RocketTile.scala
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@ -177,7 +177,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
def optionalMasterBuffer(in: TLOutwardNode): TLOutwardNode = { def optionalMasterBuffer(in: TLOutwardNode): TLOutwardNode = {
if (rtp.boundaryBuffers) { if (rtp.boundaryBuffers) {
val mbuf = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams.default)) val mbuf = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
mbuf.node :=* in mbuf.node :=* in
mbuf.node mbuf.node
} else { } else {