From e140893a0171da69bddabeee6749a03632a76bd9 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 31 Jul 2017 18:06:54 -0700 Subject: [PATCH] Use 1-entry queue on processor-side E-channel The cache can't sink a grant every cycle, so extra E buffering doesn't help. --- src/main/scala/tile/RocketTile.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 7323a30b..60b50738 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -177,7 +177,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p: def optionalMasterBuffer(in: TLOutwardNode): TLOutwardNode = { if (rtp.boundaryBuffers) { - val mbuf = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams.default)) + val mbuf = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1))) mbuf.node :=* in mbuf.node } else {