riscv/rocket-chip
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add IPIs and an IPI test

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IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
This commit is contained in:
Andrew Waterman
2012-05-08 22:58:00 -07:00
parent 87cbae2c8a
commit e0e1cd5d32
3 changed files with 23 additions and 9 deletions
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8
rocket/src/main/scala/dpath_util.scala
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@ -115,7 +115,7 @@ class rocketDpathPCR extends Component
val reg_status_et = Reg(resetVal = Bool(false));
val r_irq_timer = Reg(resetVal = Bool(false));
val r_irq_ipi = Reg(resetVal = Bool(false));
val r_irq_ipi = Reg(resetVal = Bool(true))
val rdata = Wire() { Bits() };
@ -174,6 +174,8 @@ class rocketDpathPCR extends Component
io.irq_timer := r_irq_timer;
io.irq_ipi := r_irq_ipi;
io.host.ipi.valid := Bool(false)
io.host.ipi.bits := wdata
when (wen) {
when (waddr === PCR_STATUS) {
@ -194,8 +196,8 @@ class rocketDpathPCR extends Component
when (waddr === PCR_COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); }
when (waddr === PCR_FROMHOST) { reg_fromhost := wdata; reg_tohost := Bits(0) }
when (waddr === PCR_TOHOST) { reg_tohost := wdata; reg_fromhost := Bits(0) }
when (waddr === PCR_SEND_IPI) { r_irq_ipi := Bool(true); }
when (waddr === PCR_CLR_IPI) { r_irq_ipi := Bool(false); }
when (waddr === PCR_SEND_IPI) { io.host.ipi.valid := Bool(true) }
when (waddr === PCR_CLR_IPI) { r_irq_ipi := wdata(0) }
when (waddr === PCR_K0) { reg_k0 := wdata; }
when (waddr === PCR_K1) { reg_k1 := wdata; }
when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }